Interactive Resolution of Encoding Conflicts using Signal Insertion and Concurrency Reduction

1. Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction based on STG Unfoldings V. Khomenko, A. Madalinski and A. Yakovlev University of Newcastle upon Tyne

2. Signal Transition Graph (STG) dsr+ lds+ dtack- lds- ldtack- ldtack+ d- d+ dsr- dtack+ Data Transceiver Device Bus d lds dsr VME Bus Controller dsw ldtack dtack

3. Encoding conflicts • pairs of semantically different states with the same binary encoding • not distinguishable at the circuit level • encoding conflicts have to be resolved before we can proceed with synthesis Transformations: • signal insertion: introduces additional internal signal (‘memory’) helping to trace the current state • concurrency reduction: introduces additional ordering constraints making some of the conflicting states unreachable • both are needed to explore a larger design space!

4. Example: CSC conflict 10000 10000 dtack- dtack- dsr+ dsr+ 01000 01000 00000 00000 lds+ lds+ ldtack- ldtack- ldtack- ldtack- ldtack- ldtack- dtack- dtack- dsr+ dsr+ 10100 10100 01010 01010 00010 00010 10010 10010 ldtack+ ldtack+ lds- lds- lds- lds- lds- lds- dtack- dtack- dsr+ dsr+ 10110 10110 01110 01110 M’’ M’ 10110 10110 00110 00110 d+ d+ d- d- dsr- dsr- dtack+ dtack+ 01111 01111 11111 11111 10111 10111

5. CSC resolution: signal insertion M’’ M’ dtack- dsr+ csc+ 010000 100000 000000 100001 lds+ ldtack- ldtack- ldtack- dtack- dsr+ 010100 101001 000100 100100 ldtack+ lds- lds- lds- dtack- dsr+ 101101 011100 101100 001100 d+ d- dsr- dtack+ csc- 011111 111111 101111 011110

6. CSC resolution: concurrency reduction 10000 dtack- dsr+ 01000 00000 lds+ ldtack- ldtack- ldtack- dtack- dsr+ 10100 01010 00010 10010 ldtack+ lds- lds- lds- lds- lds- dtack- dtack- dsr+ dsr+ 10110 M’’ M’ 01110 10110 10110 00110 00110 d+ d- dsr- dtack+ 01111 11111 10111

7. Framework for visualisation & interactive resolution of encoding conflicts • manual vs. automatic resolution of coding conflicts • automatic  can produce sub-optimal solutions • manual  crucial for finding good (low-latency, compact & elegant) synthesis solutions • interactivity is good! visualisation concepts: emphasise essential information avoid information overload

8. STG unfolding • partial order model • infinite acyclic net, simple structure • finite complete prefix • finite initial part of unfolding • contains all the reachable states • alleviates state space explosion problem • more visual then state graphs • proven efficient for model checking

9. State Graphs vs. Unfoldings dtack- dsr+ 10000 e1 01000 dsr+ 00000 lds+ e2 ldtack- ldtack- ldtack- lds+ dtack- dsr+ e3 core 10100 ldtack+ 01010 00010 10010 e4 d+ ldtack+ lds- lds- lds- e5 dtack+ dsr+ dtack- M’’ 10110 M’ 01110 10110 e6 00110 dsr- d+ e7 d- d- dtack+ dsr- dtack- e9 e8 lds- M’’ 01111 11111 10111 e10 e11 ldtack- dsr+ e12 lds+ M’

10. Visualisation of conflicts: Height map Core1 Core2 Core3 A1 A2 A3 • cores often overlap • high-density areas are good candidates for signal insertion • analogy with topographic maps

11. Height map: an example Highest peak csc+ Core map Height map

12. Resolution of encoding conflicts t+ Core t- Signal insertion: • insert t+ in a core • t- must be added outside the core preserving consistency • inserted transitions must not trigger an input signal

13. Concurrency reduction u1 u2 t (non-input) Add a token if needed • addition of causal constraint, i.e. a new place

14. Resolution of encoding conflicts Forward concurrency reduction: • bringing forward the ending point of concurrency • ‘dragging’ f into the core

15. Resolution of encoding conflicts Backward concurrency reduction: • delaying starting point of concurrency • ‘dragging’ f into the core

16. Resolution of encoding conflicts p’ Concurrency reduction: an example backward forward backward inputs: b,c,f; outputs: a,d,e inputs: a,b; outputs: c,d,e

17. Overview of the resolution process phase 2 concurrency reduction signal insertion phase 1

18. Cost function cost = α1· + α2·logic –α3·core • : estimated delay caused by transformation • logic: estimated increase in complexity of logic • core: number of eliminated cores, • αi: parameters chosen by the designer Calculated on the original unfolding prefix

19. Validity • signal insertion: well-developed, e.g. weak bisimulation • concurrency reduction: more challenging, e.g.: • not even language-equivalent • events can become dead • introduction/disappearance of deadlocks

20. Validity aspects • I/O interface preservation • the interface between circuit and its environment should be preserved • conformation • no “wrong” behaviour should be introduced • liveness • no “interesting” behaviour should be completely eliminated • technical restrictions • boundedness, speed-independence, etc.

21. Validity notion • natural to use partial order framework when speaking about concurrency reduction! • plan: • define a “valid realisation” relation on partial order analog of traces (processes) • define “valid realisation” relation on systems

22. Validity notion: processes a b a b  c c d d • can easily eliminate silent actions (e.g. internal signals) preserving causality – abstraction

23. Validity notion: processes • step 1: increasing concurrency of inputs • step 2: decreasing concurrency of outputs

24. Validity notion: processes i1 o i1 i2 o i2 o1 i o1 o2 i o2 • step 1: increasing concurrency of inputs • step 2: decreasing concurrency of outputs

25. Validity notion: processes i1 o i1 i2 o i1 i2 o i2 o1 o1 o1 o1 i1 i i1 i o1 o2 i o2 o2 i1 i2 o2 i2 o1 o2 i2 o2

26. Validity notion: systems E (original) E e E’ E’ (transformed) (original) e’ (transformed) • valid realisation:

27. Validity notion: systems -1 -1 o o o o1 i1 o2 i2 … o o o1 i1 o2 i2 o1 i1 i2 o2 … -1 o

28. Case study: AD converter controller Core map

29. Conclusions • combined framework for resolution of encoding conflicts based on cores in the STG unfolding • larger design space – exploit the area/delay trade-off • novel validity condition Future work • more automation • improving cost function • performing transformation directly on the unfolding prefix rather than the STG