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MuTRG-FEE Upgrade

MuTRG-FEE Upgrade. RIKEN/RBRC Itaru Nakagawa. High Momentum Muon Trigger. MuID rejection in 200GeV and 500GeV. rejection (MuID&BBC/BBC(nvtx)). 200. 150. 100. 50. 0. 0. 0.5. 1.0. 1.5. 2.0. MHz. BBC(nvtx) (estimated from ZDC narrow). σ(tot)=60mb, L=2x10 32 cm -2 s -1 (500GeV)

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MuTRG-FEE Upgrade

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  1. MuTRG-FEE Upgrade RIKEN/RBRC Itaru Nakagawa

  2. High Momentum Muon Trigger MuID rejection in 200GeV and 500GeV rejection (MuID&BBC/BBC(nvtx)) 200 150 100 50 0 0 0.5 1.0 1.5 2.0 MHz BBC(nvtx) (estimated from ZDC narrow) • σ(tot)=60mb, L=2x1032cm-2s-1 (500GeV) • collision rate = 12MHz • DAQ rate limit < 2Hz (for muon Arm) • Therefore, required rejection factor -> 6000 • Loosing MuID rejection power as a function of rates 2

  3. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Trigger MuTr FEE Interaction Region Rack Room

  4. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes MuTr FEE 95% Interaction Region Rack Room

  5. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  6. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  7. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  8. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System (RUN9) Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board RPC FEE DCM DCM MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG DCM MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  9. Prototype RPC MuTRG MuTRG W Trigger Instrumentationin RHIC 2009 run • Full Installation to North Arm, 1/2 octant install to South • Demostrait performance of RPC and MuTRG with beam of s=500 GeV.

  10. Installed New MuTRIG-FEE

  11. Noise Performance of MuTR before/after MuTRG-ADTX Install installed plane installed plane Oct.1 black: before install red: after install Oct.8 Gap.1 Pl.1 Gap.1 Pl.2 Gap.2 Pl.1 Gap.2 Pl.2 pedestal RMS value vs strip number (North, St.3) 11

  12. MuTrig Performance

  13. Efficiency for MIP (MuTRG) Efficiency ~ 100% at Plateau Turn on Point of Efficiency Curve ~ 4 Most Probable Value of MIP ~ 20 MuTRG and MuTr have matching properly. Efficiency for MIP is 97.5% (Yellow / Blue) Blue : MIP dist. Yellow : MIP x Eff. Analysis by Yoshi Fukao

  14. Threshold Dependence Analysis by Yoshi Fukao

  15. Rejection Power Analysis by Yoshi Fukao

  16. Efficiency vs. RP Analysis by Yoshi Fukao

  17. Background Issues Analysis Done by Tsutomu Mibe, KEK

  18. Rates per strip at 500 GeV (CLK trig) Average Station 3 Station 1 Station 2 Maximum Station 3 Station 2 Station 1 18

  19. Why this is bad? MuTr cathode signal Baseline-baseline ~10 msec Rate >100kHz at BBC=1MHz in 500GeV pp.  Pile-up regime ! Big pulse cause cross Talks btwn strips? 19

  20. Optical Alignment System Intrinsic MuTR Resition ~100 m Presentry 200 ~ 300m ` Yuki Ikeda and Kazufumi Ninomiya, Rikkyo University

  21. OASys Monitoring Thru Run09 IR Temperature Motion to phi Motion to r

  22. Vector and Magnitude of Motion

  23. Magnet On/Off

  24. MuTRG MuTRG RPC RPC RPC Final Configuration 2009 Full Install to South Arm

  25. Readyness for South Installation

  26. Summary • Completed North Installation and Commissioned in Run09 • Trigger Logic Test with Beam including LL1 can be done in Run10 • South Arm Installation Ongoing • Optimization of Operating Condition is under study. More Efforts Required to achieve Higher Rejection Power • Background Study • Improving MuTR Resolution Efforts also underway

  27. Backup Slides

  28. MuTRG system performance MuTRG efficiency vs MuTR charge plateau efficiency rate (Hz) Blue : MIP dist. Yellow : MIP x Eff. MuTR charge dist. • Important parameter for trigger system • efficiency • rejection factor • (MuTRG&MuID&BBC)/(MuID&BBC) 28

  29. Muon Tracker fast track selection (MuTRG) B Local Level-1 trigger board (LL1 board) ADC ADC ADC Level-1 trigger Data Collecting Module (DCM) MuTRG-ADTX fast digitalized hit signal fast digitalized hit signal fast digitalized hit signal Quark polarization, W boson measurement at PHENIX Quark polarization, W boson measurement at PHENIX 2014/9/22 29

  30. A possible cross talk senario Particle hit the chamber and generate a electron-ion pairs in chambers. Electrons are collected by anode wire(s). It induces charge in near-by cathode strip(s) Collected anode charge does not have any path to escape in the anode circuit (high impedance). Other cathode strips induce same-sign charge in the strips, thus opposite sign charge in anode. After shaping, FEE sees cross-talk signals in opposite phase. +HV GND 30

  31. Hit distribution (200 GeV, zerosup OFF) Gap 1 Stereo Gap 2 Stereo Gap 3 Stereo Pedestal – ADC(3) Gap 1 NonStereo Gap 2 NonStereo Gap 3 NonStereo Strip mutr_strip_event000978_clk2424488676q 31

  32. Saggitta

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