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The CLEO-c Trigger System: More Than Just Blinking Lights ! LEPP Lunch Talk Mats Selen

The CLEO-c Trigger System: More Than Just Blinking Lights ! LEPP Lunch Talk Mats Selen. Overview Tracking Calorimeter Timing Performance. You are the trigger: You stamp “y” on the pink hexagonal widgets You stamp “n” on the others. Your friend DAQ saves only widgets labeled “y”. Trigger.

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The CLEO-c Trigger System: More Than Just Blinking Lights ! LEPP Lunch Talk Mats Selen

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  1. The CLEO-c TriggerSystem:More Than Just Blinking Lights !LEPP Lunch TalkMats Selen • Overview • Tracking • Calorimeter • Timing • Performance

  2. You are the trigger:You stamp “y” on the pink hexagonal widgets You stamp “n” on the others Your friend DAQsaves only widgetslabeled “y” Trigger DAQ y/n y n y n y SAVE n trash What the Trigger & DAQ Does Suppose you want to keep only pink hexagonal widgets moving down a conveyor belt. The problem is:Working fast means you make some mistakes !

  3. Requirements: Decision Time Each widget must get examined and stamped - You need to decide on one before the next one comes along. - Your decision can’t take longer than Dt = d/v. - Taking more time means making less mistakes. Trigger d y/n y n y n v

  4. Requirements: Efficiency You can’t stamp too many pink hexagonal widgets”n”: Trigger DAQ ? ? ? y/n n n n n SAVE n n n trash

  5. Requirements: Rejection The rate of widgets stamped “y” can’t exceed the capacity of your friend (the DAQ) to save them. Whenever the DAQ is busy saving something it causes “dead-time” (he will miss the next few widgets). If he misses any marked “y”, thiscauses a loss of efficiency. Trigger DAQ y/n y y y y y SAVE y trash

  6. y/n Working in Steps: Pipelining Have more than one person working in series - Each individually one takes less than Dt = d/v- Collectively, much more work is done- A smarter decision can be made – less mistakes Trigger DAQ d y n y n y v SAVE n trash

  7. 14 feet 800 feet d = 14 feet, v = 1 foot/ns  Dt = 14 ns There are 183 RF buckets in CESR

  8. The trigger runs at1/3 the CESR RF freq(i.e. each step is 42 ns) Only ~45 of thesebuckets contain beam ‘bunches’ In CESR/CLEO, beam collisions arespaced a minimum of 14 ns apart. This smears together 3 beam collisions every time we look. We can do this since its very rare that anything happens during a collision. This is not enough time to do any serious trigger processing

  9. 3 2 1 0 60 59 58 0 1 2 3 . . . . . . 58 59 60

  10. 3 2 1 0 60 59 58 0 1 2 3 . . . . . . 58 59 60

  11. More about thisin a few minutes 0 1 2 3 . . . . . . 58 59 60

  12. 72 MHz RF bucket 24 MHz Pipeline clk Early DR Late DR Early CC Late CC look here for DR info look here for CC info Suppose eventhappens here Trigger Philosophy • Use only drift chamber (DR) and calorimeter (CC) information. • Make trigger decision every 42ns (i.e. trigger clock rate). • Take enough time (number of pipelined steps) to make a sophisticated Level-1 trigger decision: About 2 ms. • The readout deadtime is about 20 ms, so we need to keep the trigger rate < 1000 Hz.

  13. Mixer/Shaper Crates (24) Drift Chamber Crates Gates CLEO Mixer/Shaper Boards ctrl. DR3 - TQT G / CAL TILE (16) AXTR(16) AXX(16) Flow control & Gating DFC DAQ ASUM Analog TIM TIM Barrel CC Axial tracker QVME DM/CTL DM/CTL TILE(8) STTR(12) L1D ASUM Stereo tracker Endcap CC QVME TIM DM/CTL Level 1 decision AXPR TRCR CCGL TRCR CC Digital TPRO(4) TIM SURF SURF TPRO(2) DM/CTL TCTL TIM DM/CTL CLEO-III/cTriggerSystemOverview

  14. What it Looks Like(all more or less alike to untrained eye)

  15. Inputs FPGA based Logic Outputs Circular Buffer DAQ/ VME TDI TMS TCK TDO JTAG Common Feature

  16. Axial Tracking Trigger 16 AXX receiver boards 16 AXTR trigger boards Repeating unit (x 8) 106 x 2 • 7 LVDS from DR3 preamps track info to TRCR backplane (single ended)

  17. Layer 9 = “key” InnerLookup OuterLookup Inner/Outer track correlator

  18. Stereo Tracking Trigger There are too many wires to form allcombinations in LUT- Combine these into 4x4 blocks

  19. stereo trigger hardware 8 8 8 TQT TQT 8 r 48 48 f 1 superlayer

  20. Track in U and V Independently = Hit wire location at z = 0 f-shifted curve, Pperp = 350 MeV/c q = 35o f = 17o Track trajectory: Pperp = 350 MeV/c q = 35o f = 15o

  21. Axial – Stereo Correlation

  22. Axial – Stereo Correlation

  23. Axial Raw key wires 112 Clustered key wires 112 Axial matching cells 48 Stereo - U 48 high 48 low Stereo - V 48 high 48 low high low high Axial - Stereo Correlation

  24. Energy sharing between boards can result in a loss of efficiency: Threshold = 500 MeV contained shower Simulated Efficiency Present summing = Tile summing = Calorimeter Trigger

  25. Wrinkle – We need to work fast! Preamp out twice differentiated Mixer/shaper out Trigger signal Discriminator out 2 ms/div Calorimetertrigger information comes ~ 1.8 us after crossing.

  26. low med high 1 m/s crate 1 m/s card   “Tiling” sets too many bits  Must Sparsify

  27. low med high H M L 01 11 10 11 proj 01 11 11 10 Availableto decisionboards 11 H M L proj SH 011 SM 001 SL 001 L1-D Crate

  28. CC time – TR time LOW Time Bucket 5 20 10 15 10 20 MED 30 40 Key Wire 50 60 HIGH 70 80 90 100 110 #track Ev-time Timing Issues

  29. That’s how thisplot is made ! 0 1 2 3 . . . . . . 58 59 60

  30. Compare to Simulation (1995) Mean = 17.5 RMS = 0.73 Mean = 16.9 RMS = 0.51 1 track events 4 track events Trigger Time (42ns bucket) Trigger Time (42ns bucket) Mean = 16.7 RMS = 0.41 Mean = 16.6 RMS = 0.37 7 track events 10 track events Trigger Time (42ns bucket) Trigger Time (42ns bucket)

  31. Pipe-delay MAKE 48 MATCHING CELLS From AXTR Pipe-delay Back-plane AXIALCELLCOUNT Pipe-delay FIND EVENTTIME For timealignment CB & DAQ Typical Trigger Board

  32. From AXTRCrate AXPR TRCR-1 From STTRCrate L1D Trigger Crate TRCR-2 From TPROCrate CCGL L1D To DAQ LUMI

  33. Trigger Decision Boards (L1D) 48 24 24 Route Prescale Bunch LUT 8 FPGAs Info (185) L1-accept Backplane Timing (3) Scaler Info (valid at timing edge) Timing (TR, CB or CE)

  34. How To Define a CLEO-c Trigger Line % Generic Hadron Line, Barrel Timing % SUBDESIGN line0( in[117..0] : INPUT; out : OUTPUT; ) Variable 1cblow : SOFT; 3tracks : SOFT; evtime : SOFT; Begin -- trigger bit mappings: tr_time[1..0] = in[1..0]; cb_time[1..0] = in[3..2]; ce_time[1..0] = in[5..4]; cc_time[1..0] = in[7..6]; tr_n_hi[3..0] = in[11..8]; tr_n_lo[3..0] = in[15..12]; tr_n_ax[3..0] = in[19..16]; tr_lowpos[1..0] = in[21..20]; cb_l_phi[7..0] = in[29..22]; cb_h_phi[7..0] = in[37..30]; cb_low_old[1..0] = in[39..38]; cb_med_old[1..0] = in[41..40]; cb_high_old[1..0] = in[43..42]; ce_low_old[1..0] = in[45..44]; ce_med_old[1..0] = in[47..46]; ce_high_old[1..0] = in[49..48]; cb_n_low[2..0] = in[52..50]; cb_n_med[2..0] = in[55..53]; cb_n_high[2..0] = in[58..56]; ce_n_low[2..0] = in[61..59]; ce_n_med[2..0] = in[64..62]; ce_n_high[2..0] = in[67..65]; bha_theta[7..0] = in[75..68]; cc_spare[15..0] = in[91..76]; cpu_trig[1..0] = in[93..92]; control[23..0] = in[117..94]; ---------------------------------------------- -- trigger line definition 1cblow = cb_n_low[] > 0; 3tracks = (tr_n_hi[]>2) # ((tr_n_hi[]>1)&(tr_n_lo[]>0)) # ((tr_n_hi[]>0)&(tr_n_lo[]>1)) ; evtime = cb_time[0]; out = 1cblow & 3tracks & evtime; End;

  35. No Trigger - hardware Axial TriggerPerformance All Tracks PT 1/PT 1/PT “Non-Isolated Tracks” In Hadron Events No Trigger -missing hits 200 MeV Total Efficiency 1/PT 1/PT

  36. Stereo TriggerPerformance(with axial) All Tracks “IsolatedElectronTracks” No Trigger B = 1.5 T Total Efficiency 210 MeV 1/PT

  37. Stereo TriggerPerformance(with axial) All Tracks “IsolatedElectronTracks” No Trigger B = 1.0 T Total Efficiency 140 MeV 1/PT

  38. Needsmorestudy CC Trigger Performance 1.0 .8 .6 .4 .2

  39. For Lots More Info http://www.hep.uiuc.edu/cleo/trig3/

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