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CRKIT R5 Architecture rev 0.1

CRKIT R5 Architecture rev 0.1. WINLAB – Rutgers University April 25, 2013 Khanh Le, Prasanthi Maddala, Ivan Seskar. R5 Architecture Summary. Support of Zynq platform Support of new RF. R5 Architecture Summary. R4 - app2host. if (IP == 1) then

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CRKIT R5 Architecture rev 0.1

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  1. CRKIT R5 Architecturerev 0.1 WINLAB – Rutgers University April 25, 2013 Khanh Le, Prasanthi Maddala, Ivan Seskar

  2. R5 Architecture Summary Support of Zynq platform Support of new RF

  3. R5 Architecture Summary

  4. R4 - app2host if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP) else Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP) endif Lookup using PortID dMAC/Ethertype from IP Processor VRT Receiver Lookup using PortID dMAC/Ethertype appended to IP/VITA data if (V == 1) then Enable VITA formatting else Disable VITA formatting endif

  5. R4 - app2host MMU drdy - data ready dreq - data request Use CMD_CNT as ACK to MEM_CTL/PCORE to indicate completion of data removal from MEM. CMD FORMAT PortID: 0-3 - APP0-3 ports 4-15 – PCORE ports size : data size in bytes ptr : pointer to data in memory To prefetch configuration settings at VITA emitter and IP Processor. Next prefetch can commence during current payload transfer

  6. R4 - host2app PCORE CMD FORMAT Ethertype = 0x0800 - IPv4 0x0806 - ARP If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM. Forward ethernet payload if : • incoming MAC = dMAC • incoming MAC = Broadcast Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE

  7. R4 - PCORE PCORE – RMAP RD/WR IP Host -> PCORE (UDP-1001) RTYPE: 0x2000 – RMAP READ 0x2001 – RMAP WRITE RADDR: Register address RDATA: Register data Address Decoding IP PCORE -> Host (UDP-1001)

  8. R4 - APP

  9. R4 – Memory Map Upper 4 MSBs : 0x0-0x1 : PCORE 0x2 : CRKIT Others : Unused 0x0 : CMN 0x1 : ETH 0x2 : PKT 0x4-0xB : APP 0xC : DAC IF 0xD : ADC IF INT SPI, LED DCM/CLOCK CE

  10. R4 – Interrupt Architecture CMN INT ETH INT PKT INT uP INTC IPIF APP INT SYS INT PCORE CR

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