Efficient Analytical Determination of the SEU-induced Pulse Shape

1. Efficient Analytical Determination of the SEU-induced Pulse Shape Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station, TX

2. Radiation Particle Strike • What is a radiation particle strike? • Neutron, proton and heavy cosmic ions • Ions strike diffusion regions • Deposit charge • Results in a voltage spike • Can result in a logical error – Single Event Upset (SEU) or Soft Errors • Radiation particle strike is modeled by a current pulse as where: Q is the amount of charge deposited ta is the collection time constant tb is the ion track establishment constant

3. Outline • Introduction • Previous Work • Approach • Classification of Radiation Particle Strikes • Our Model • Experimental Results • Conclusions

4. Introduction • Modern VLSI Designs • Vulnerable to noise effects- crosstalk, SEU, etc • Single Event Upsets (SEUs) or Soft Errors • Troublesome for both memories and combinational logic • Becoming increasingly problematic even for terrestrial designs • Applications demand reliable systems • Need to efficiently design radiation tolerant circuits • Selectively harden sensitive gates in a circuits • Gate which significantly contribute to soft error failure rate of circuit

5. Introduction • 3 masking factors determine sensitivity of gates • Logical, temporal and electrical masking • Logical and temporal can be obtained without electrical simulations • Electrical masking need electrical simulations • Depends upon on the electrical properties of all gates on sensitized path from gate to primary outputs (POs) • Important to consider these factors for efficient circuit hardening • Need efficient analysis and simulation approaches • Analyze circuits early in design flow • Based on the results of the analysis, we can efficiently achieve required tolerance while minimizing overheads

6. SEU Simulation and Analysis • Electrical masking effects can be determined by SPICE based simulation of SEU events • Most accurate circuit simulation possible • Computationally expensive • Too many scenarios required to be simulated • Amount of charge dumped • State of circuit inputs • Need to simulate all nodes in a circuit • Hence we need an efficient and accurate approach to determine the shape of the radiation induced voltage glitch • This is the focus of this talk

7. Previous Work • Device-level simulation: Dodd et. al 1994, etc • Accurate but very time consuming • Not helpful for circuit hardening • Logic-level simulation: Cha et. al 1996 • Abstract transient faults by logic-level models • Gate-level timing simulators are used • Highly inaccurate • Circuit-level simulation: • Intermediate between device and logic level simulation • However, this is still very time consuming since a large number of scenarios need to be modeled

8. Previous Work • Shih et. al 1992 solve transistor non-linear differential equation using infinite power series • Computationally expensive • Dahlgren et. al 1995 presented switch level simulator • Electrical simulations are performed to obtain the pulse width of a voltage glitch for given R and C values of a gate • Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the newR and C values • Cannot be used for different values of Q • Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits • Linear RC gate model is used • Ignores the contribution of tb in iseu(t) – we found that this results in 40% root mean square percentage error in voltage glitch • Both these factors result in higher inaccuracy. • Our approach has a 4.5% error

9. Objective • Develop an analytical model for waveform of a radiation-induced voltage glitch in combinational circuits • Closed form analytical expression for the pulse shape of voltage glitch • Accurate and efficient • Applicable to • Any logic gate • Different gate sizes • Different gate loading • Incorporates the contribution of the tb time constant • Can be easily integrated in a design flow • Can be used with a glitch propagation tool to evaluate the effect (at the circuit Primary Outputs) of a radiation strike at any internal gate G • So we can find (and harden) sensitive gates in a design

10. Our Approach • Consider a radiation particle strike at the output of INV1 • Implemented using 65nm PTM with VDD=1V • Radiation strike: Q=150fC, ta=150ps & tb=50ps M1 in Saturation M2 in Saturation M2’s Drain-Bulk diode is ON M1 in Saturation M2 in Saturation Models Radiation Particle Strike M1 in Saturation M2 in Cutoff M1 in Linear M2 in Cutoff M1 and M2 operate in different regions during radiation-induced transients We estimate the radiation-induced voltage waveform by modeling these regions INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches)

11. Classification of Radiation Strike • INV1 can operate in 4 different cases depending upon voltage glitch magnitude VGM (=Va) • Case 1: VGM ≥ VDD + 0.6V • Case 2: VDD+|VTP| ≤VGM < VDD + 0.6V • Case 3: 0.5*VDD ≤VGM <VDD+|VTP| • Case 4: VGM < 0.5*VDD Different analytical models are applicable to different cases to compute pulse waveform of the voltage glitch

12. Model Overview Given a gate G, its input state, the gates in the fanout of G and Q, ta and tb Cell library data Iout(Vin,VDS) for VGS=1 and 0, CG and CD Determine the value of VGMusing gate current model for Vdsat ≤ Va ≤ VDD – V|TP| If Case==4 If Case==3 No voltage glitch Use Case 3 equations to estimate the shape of voltage glitch Yes No Yes No Determine the value of VGMusing gate current model for Va ≥ VDD – V|TP| If Case==2 Use Case 1 equations to estimate the shape of voltage glitch Use Case 2 equations to estimate the shape of voltage glitch No Yes

13. Voltage Glitch Magnitude (VGM) • Load current model of INV with input at VDD • Differential equation for radiation induced voltage transient at output of INV1 (1) Green  Known Yellow  Unknown Va(t) VGM Again integrate Equation 1 with initial condition (Vdsat, T1sat) and with Integrate Equation 1 from (0, 0) to (Vdsat, T1sat) with Now VGM = Va(TVGM) Vdsat Obtain TVGMby differentiating Va(t) and solving dVa(t)/dt = 0 If VGM > 0.5*VDD then there is a glitch Solve for T1sat T1sat TVGM t If 0.5*VDD ≤ VGM < VDD + |VTP| then Case 3 is applicable otherwise need to resolve between Case 1 and Case 2

14. Derivation for Case 3 • For Case 3: 0.5*VDD ≤ VGM < VDD + |VTP| • PMOS transistor never turns ON • Already know voltageexpressions for time intervals(0 ,T1sat) and (T1sat ,T2sat) (1) Green  Known Yellow  Unknown Va(t) VGM Vdsat Integrate Equation 1 from with (Vdsat, T2sat) as initial condition with T1sat TVGM t T2sat Solve for T2sat Now, the voltage expression is available for t = T2sat to infinity also

15. Resolving Between Cases 1 and 2 Green  Known Yellow  Unknown Va(t) VGM VDD + |VTP| Integrate Equation 1 from with (VDD+V|TP|, T1P) as initial condition with Now VGM = Va(TVGM) Vdsat t T1sat T1P TVGM Obtain TVGMby differentiating Va(t) and solving dVa(t)/dt = 0 If VDD + V|TP| ≤ VGM <VDD + 0.6 then Case 2 is applicable otherwise Case 1 is applicable Solve for T1P *Details can be found in the paper VGM > VDD + |VTP| Need to re-compute VGM to resolve between Cases 1 and 2 Find T1P when Va(t) = VDD + V|TP|

16. Derivation for Case 2 Green  Known Yellow  Unknown Va(t) VGM VDD + |VTP| Integrate Equation 1 from with (VDD+V|TP|, T1P) as initial condition with Vdsat t T1sat TVGM T1P T2P T2sat Solve for T2P Solve for T2sat For Case 2: VDD + V|TP| ≤ VGM < VDD + 0.6 Diode never turns ON Already know voltage expressions for time intervals (0 ,T1sat),(T1sat ,T1P) and (T1P ,T2P) Solve for T2P Also known for (T2P, T2sat) Solve for T2sat Now integrate Equation 1 with initial condition (Vdsat, T2sat) similar to Case 3

17. Derivation for Case 1 For Case 1: VGM ≥ VDD + 0.6V Diode turns ON and clamps the node voltageto VDD + 0.6V Derivation is similar to Case 2 For (T1P, T2P) the voltage expression is modified to min(VDD + 0.6, Va(t)) Voltage expression for other time intervals are same as that of Case 2

18. Experimental Results • Implemented our model in Perl • Applied our model to INV, NAND2 and NOR3 • Using 65nm PTM model card with VDD=1V • Characterized each gate for IDS, CG and CD • For each of these gates, we applied our model • For different values of Q, ta and tb • Different gate sizes and loads • Our model is ~275X faster compared to SPICE • Results could be improved if implemented in a compiled language

19. Experimental Results

20. Experimental Results • Root mean square percentage (RMSP) error for 3X gates for Q=150fC, ta=150ps and tb= 50ps

21. Experimental Results • RMSP error averaged over all possible input states for different gate sizes for Q=150fC, ta=150ps and tb= 50ps • Average RMSP error of our model is 4.5% • Much lower than 40% error of the model by Mohanram 2005

22. Conclusion • We presented an analytical model to estimate the shape of the radiation-induced voltage glitch • Can be used with glitch propagation tools to estimate the voltage glitch at POs • Based on this, sensitive gates can be identified and hardened to improve the radiation tolerance of the design • This can be done early in the design cycle • Our model is accurate and efficient • RMSP error is 5% compared to SPICE • Our method is 275X faster than SPICE • Our model gains accuracy • By using the load current model (and avoiding a linear RC model for the gate) • By including the contribution of tb

23. Thank You