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Logic Circuit Design

Logic Circuit Design. Yawgeng Chau. Contents. Binary Systems Boolean Algebra and Logic Gates Gate-Level Minimization Combinational Logic Synchronous Sequential Logic Registers and Counters Memory and Programmable Logic. 5.1 Sequential Circuits. Sequential circuits consist of

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Logic Circuit Design

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  1. Logic Circuit Design Yawgeng Chau

  2. Contents • Binary Systems • Boolean Algebra and Logic Gates • Gate-Level Minimization • Combinational Logic • Synchronous Sequential Logic • Registers and Counters • Memory and Programmable Logic Logic Circuits

  3. 5.1 Sequential Circuits • Sequential circuits consist of • Input, logic gates, output, storage elements • State of storage elements is a function of past input • Output depends on current and past inputs. • State: binary information stored in memory • Sequential circuit is specified by • A time sequence of inputs, outputs, and internal states. Logic Circuits

  4. 5.2 Synchronous vs. Asynchronous • Synchronous Sequential Circuit • Function according to its inputs and states at discrete instants of time. • Asynchronous Sequential Circuit (Ch. 9) • Function according to its inputs and states at discrete instants of time and the input changing order. • May become unstable due to feedback. Logic Circuits

  5. Synchronous Clocked Sequential Circuit • Use clock generator to generate a periodic train of clock pulses. • Storage elements are activated when a clock pulse arrives. • States can change during pulse transition. Logic Circuits

  6. Flip-Flops as storage elements • Flip-flop : binary storage device to store 1bit. Logic Circuits

  7. S=1 Set State 5.3 SR Latch with NOR Gates • S or R must go back to 0 before further changes to avoid undefined states. • 1 should not on S and R at the same time. R=1 Reset State Forbidden Logic Circuits

  8. R=0 Reset State SR Latch with NAND Gates • S or R must go back to 1 before further changes to avoid undefined states. • 0 shouldn't go on S and R at the same time. S=0 Set State Forbidden Logic Circuits

  9. SR Latch with Control Input • Enable signal is used to determines when the state of the latch can be changed. En=1: enable; En=0: disable Logic Circuits

  10. D Latch • To ensure that S and R never equal to 1 at the same time. • Transparent latch: temporary bit storage Logic Circuits

  11. Graphic Symbols SR Latch with NAND gates NOR gates Logic Circuits

  12. Latch Problem from Feedback (1/2) Unpredictable results if En=1 with changing D Logic Circuits

  13. Latch Problem from Feedback (2/2) • Latch state changes once the clock pulse changes to 1. • New latch state appears at the output while the pulse is active. • The output works on the latch input through combinational feedback. • If inputs change while the clock pulse is in 1, the latch will respond and result in new outputs. Logic Circuits

  14. 5.4 Flip-Flops (1/2) • Flip-Flop (FF): a memory element changes at the edge of clock only • If level-triggered flip-flops are used • The feedback path may cause instability problem • Edge-triggered flip-flops • The state transition happens only at the edge • Eliminate the multiple-transition problem Logic Circuits

  15. Flip-Flops (2/2) • Trigger : Change in control input. • Triggered only during a signal transition. Level trigger Positive trigger or rising-edge trigger Negative trigger or falling-edge trigger Logic Circuits

  16. D Flip-Flops Q(t+1)=D • Work as D-latch, but edge-trigger Characteristic Table D Q(t+1) 0 0 1 1 Fig. 5.11 Graphic symbols foredge-triggered D flip-flop Logic Circuits

  17. Master-Slave D Flip-Flop (1/2) • Negative-edge trigger Master: DY Slave: Q doesn’t change Y doesn’t change YQ Logic Circuits

  18. Master-Slave D Flip-Flop (2/2) • How to make it be a positive-edge triggered flip-flop? Logic Circuits

  19. D-Type Positive-Edge Triggered Flip-Flop • Initially, CLK=0, S=1,R=1; Q(t+1)=Q(t) • When CLK1 as D=0, R0, Q=0 • If D changes to 1 when CLK=1, R=0 because Q=0 • When CLK1 as D=1, S0, Q=1 • If D changes to 0 when CLK=1, S=0. Logic Circuits

  20. Time Parameters • Setup Time: minimum time such that D must be maintained at a constant value before clock transition. • Hold Time: minimum time such that D does not change after the positive clock transition. • Propagation Delay Time: time from trigger edge to the time of a stable output. Logic Circuits

  21. JK Flip-Flop J K Q(t+1) 0 0 Q(t) Hold 0 1 0 Reset 1 0 1 Set 1 1 Q'(t) Toggle Q(t+1)= D = JQ(t)' +K'Q(t) Logic Circuits

  22. T Flip-Flop T=0, D=Q(t) , Q(t+1)=Q(t) T=1, D=Q'(t) , Q(t+1)=Q'(t) T=0, J=K=0, Q(t+1)=Q(t) T=1, J=K=1, Q(t+1)=Q'(t) T Q(t+1) 0 Q(t) Hold 1 Q'(t) Toggle Q(t+1)=TQ(t) Logic Circuits

  23. Characteristic Tables Logic Circuits

  24. Characteristic Equations K 0 1 J 0 1 Q(t+1)=J'K'Q+JK'+JKQ'=J'K'Q+JK'Q+JK'Q'+JKQ' = K'Q+JQ' Logic Circuits

  25. Preset& Clear (Reset) • Asynchronous input R=0 clear; R=1 undo 1 1 Logic Circuits

  26. 5.5 Analysis • Given a sequential circuit, we try to guess what it is. • Step 1: write the excitation equations or the state equations • Step 2: draw the state table • Step 3: draw the state diagram • Step 4: guess… • All red keywords have the same meaning. Logic Circuits

  27. Flip-Flop Input/Output Equations flip-flop input DA =Ax+ Bx DB =A'x y = (A+B)x' DA flip-flop name Step 1 (way 1) Compute input equation (or called excitation equation) & output equation Logic Circuits

  28. Next-State Derivation Step 1 (Way1) : determine input equations (or excitation equations) using present states and input variables. Step 2: list all binary combination of inputs/state. Use characteristic table to determine next state values and create the state table. Logic Circuits

  29. State Equations A DA=Ax+Bx x Step 1 (way 2) x excitation or input equation B DA =A x +B x DB = A' x output equation y = (A+B)x' A' DB=A'x characteristic equation x Q(t+1)=D state equation A(t+1) = DA =A x +B x B(t+1) = DB = A' x B y=x'(A+B) A x' x Logic Circuits

  30. State Table (1/2) Step 2 Draw the state table (form 1) DA =Ax+ Box DB =A'x y = (A+B)x' (1) excitation equ. DADB A B 00 01 00 11 00 10 00 10 00 01 00 11 00 10 00 10 (2) state equ. A(t+1)= Ax+ Bx B(t+1)= A'x y(t) = (A+B)x' Logic Circuits

  31. State Table (2/2) Step 2 Draw the state table (form 2) Logic Circuits

  32. State Diagram Step 3 Draw the state diagram AB State Mealy Machine Logic Circuits

  33. Example of D Flip-Flop Step 1 excitation equation or state equation DA=Axy xy Step 2 state table Step3 state diagram Logic Circuits

  34. Example of JK Flip-Flop (1/3) Step 1 excitation equation JA= B KA=Bx' JB= x' KB=Ax JA=B x' KA=Bx' B JB=x' A KB=Ax x Logic Circuits

  35. Example of JK Flip-Flop (2/3) Step 2 state table JA= B KA=Bx' JB= x' KB=Ax Logic Circuits

  36. State Equations Derived with Characteristic Equations and Input Equations characteristic equation Q(t+1)= D = JQ(t)' +K'Q(t) → State equations JA=B A (t+1)= JAA' +KA'A = BA' +(Bx')'A = A'B +AB' +Ax KA=Bx' JB=x' B (t+1)= JBB' +KB'B = x'B' +(Ax)'B = B'x' +ABx +A'Bx' KB=Ax Logic Circuits

  37. Example of JK Flip-Flop (3/3) Step3 state diagram Logic Circuits

  38. Example of T Flip-Flop (1/3) x TA=Bx y=AB B Step 1 characteristic equation input/output equation TB=x state equation Logic Circuits

  39. Example of T Flip-Flop (2/3) Step 2 state table TA= Bx TB = x y = AB TATB A B 00 01 01 10 10 11 11 00 Logic Circuits

  40. Example of T Flip-Flop (3/3) Step 3 state diagram Input AB / y State/output Moore Machine Logic Circuits

  41. Mealy FSM (Finite State Machine) • Output is a function of input and present state. • For synchronized output, inputs are synchronized with the clock. • Outputs must be sampled during the clock edge. y=x'(A+B) Logic Circuits

  42. Moore FSM x TA=Bx y=AB B • Output is a function of present state only. • Outputs are synchronized with the clock. TB=x Logic Circuits

  43. 5.7 State Reduction • To reduce the flip-flop number. • May require more combinational gates. Design a ciruit: Step 1 Draw the state diagram but find the graph is complex Logic Circuits

  44. Example (1/5) state a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 Logic Circuits

  45. Example (2/5) Step 2 Draw the state table Logic Circuits

  46. Example (3/5) • States g and e are equivalent. g is replaced by e. Step 2 Find two equivalent states, replace one with another, redraw the state table Logic Circuits

  47. Example (4/5) • States f and d are equivalent. f is replaced by d. Step 3 Repeat Step 2 until you can not find any more Logic Circuits

  48. Example (5/5) Step 4 Redraw the state diagram Logic Circuits

  49. State Assignment Step 5 State assignment Redraw the state table  Logic Circuits

  50. 5.8 Simplified Design Procedure Step 1: Derive a state diagram from operation specifications. Step 2: Obtain the state table by finding the input values of flip-flops. Step 3: Derive input equations and output equations. Step 4: Draw the sequential circuit Logic Circuits

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