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Chapter 10

Chapter 10. Timing Issues. Rev.1.0 05/11/2003 Rev. 1.1 05/28/2003 Rev. 1.2 06/05/2003. R. 1. R. 2. R. 3. In. Logic. Logic. Out. D. Q. D. Q. D. Q. Block #. 1. Block #. 2. t. t. t. pd,reg. CLK. pd. 1. pd. 2. Synchronous Pipelined Datapath. Data Register.

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Chapter 10

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  1. Chapter 10 Timing Issues Rev.1.0 05/11/2003 Rev. 1.1 05/28/2003 Rev. 1.2 06/05/2003

  2. R 1 R 2 R 3 In Logic Logic Out D Q D Q D Q Block # 1 Block # 2 t t t pd,reg CLK pd 1 pd 2 Synchronous Pipelined Datapath Data Register Output Register

  3. Self-Timed Logic (Asynchronous Datapath) Check Textbook (Sec. 10.4) for details!

  4. Latch Parameters D Q Positive Latch Clk T Clk PWm tsu D thold td-q tc-q Q tc-q Delays can be different for rising and falling data transitions

  5. Register Parameters D Q Positive Edge-Triggered Register Clk T Clk thold D tsu tc-q Q

  6. 2 : Device Variations 5 : Temperature Sources of Clock Uncertainties

  7. Clock Nonidealities • Clock skew • Spatial variation in temporally equivalent clock edges: deterministic + random, • Clock jitter • Temporal variations in consecutive edges of the clock signal: modulation + random noise • Cycle-to-cycle (short-term) tJitter • Long-term tJitter • Variation of the pulse width • Important for level-sensitive clocking

  8. Clock Skew and Jitter Clk • Both skew and jitter affect the effective cycle time tSK Clk tJS

  9. Clock Skew (Distribution) # of registers Earliest occurrenceof Clk edge Nominal – /2 Latest occurrenceof Clk edge Nominal + /2 Clk delay Insertion delay Max Clk skew 

  10. Positive and Negative Skew

  11. Positive Skew Launching edge arrives before the receiving edge

  12. Negative Skew Receiving edge arrives before the launching edge

  13. Datapath Structure with Feedback

  14. Positive Skew Launching edge arrives before the receiving edge

  15. Timing Constraints Minimum cycle time ( fastest clock rate): T +  >= tc-q + tlogic + tsu Eq. (10.3) • Has the potential to improve the performance ( >0)

  16. Timing Constraints Hold time constraint: thold +  < t(c-q, cd) + t(logic, cd)  Race between data and clock   should be kept small

  17. T k n CLK t j m l CLK jitter o -t jitter Combinational REGS In Logic CLK t t , t logic t c-q c-q, cd logic, cd t t su, hold t jitter Impact of Jitter T – 2 tjitter >= tc-q + tlogic + tsu Eq. (10.5)

  18. Combined Impact of Skew and Jitter T +  – 2 tjitter >= tc-q + tlogic + tsu Eq. (10.6) thold +  < t(c-q, cd) + t(logic, cd) – 2 tjitter Eq. (10.7)

  19. Latch-Based Design L2 latch is transparent when f = 1 L1 latch is transparentwhen f = 0 f L1 L2 Logic Latch Latch Logic

  20. Latch-based Design

  21. Edge-triggered Pipeline Design

  22. Slack-borrowing (Sec. 10.3.4)

  23. Clock Distribution H-tree Clock is distributed in a tree-like fashion

  24. More realistic H-tree [Restle98]

  25. The Grid System • No rc-matching • Large power

  26. Example: DEC Alpha 21164

  27. final drivers pre-driver 21164 Clocking tcycle= 3.3ns • 2 phase single wire clock, distributed globally • 2 distributed driver channels • Reduced RC delay/skew • Improved thermal distribution • 3.75nF clock load • 58 cm final driver width • Local inverters for latching • Conditional clocks in caches to reduce power • More complex race checking • Device variation tskew = 150ps trise = 0.35ns Clock waveform Location of clock driver on die

  28. Clock Skew in Alpha Processor

  29. tcycle= 1.67ns trise = 0.35ns tskew = 50ps EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS • 2 Phase, with multiple conditional buffered clocks • 2.8 nF clock load • 40 cm final driver width • Local clocks can be gated “off” to save power • Reduced load/skew • Reduced thermal issues • Multiple clocks complicate race checking Global clock waveform

  30. 21264 Clocking

  31. ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 EV6 Clock Results GCLK Skew (at Vdd/2 Crossings) GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

  32. EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains + widely dispersed drivers + DLLs compensate static and low-frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks

  33. Summary • Clocking schemes are very important in synchronous circuit designs  dominated in speed performance and power consumption. • Clock jitter and skews should be considered in early design phase. • Phase-locked loop (PLL) and Delay-locked loop (DLL) circuits are used to reduce the clock jitter and skews. • Good clock distribution CAD tools are useful in analyzing the clock performance in modern chips.

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