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Welding next to electronics Richard French, John Matheson , Ian Wilmut May 2012. The Swagelok orbital welder Use of the orbital welder at the patch panels A lead from the literature “Destructive” testing: XCHIP, ABCN-25, ABCN-13, FEI4 EMFs induced by changing magnetic field
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Welding next to electronicsRichard French, John Matheson, Ian Wilmut May 2012 • The Swagelok orbital welder • Use of the orbital welder at the patch panels • A lead from the literature • “Destructive” testing: XCHIP, ABCN-25, ABCN-13, FEI4 • EMFs induced by changing magnetic field • Conclusions so far • What next ?
Orbital welder setup power supply weld head jig for butting tubes Nominal current waveform small weld head tungsten tip, motor driven power cables run close together
RAL services mockup Built to examine feasibility of joining pipes using orbital welder Each pipe has a joining section 2 welds per pipe Position, orientation of weld head known (or so we believe.... ) Mockup built by Mike Bell, John Hill (RAL)
Comparison with Literature -1 Electric welding hazard to spacecraft electronics, Whittlesey and Lumsden, IEEE Int Symp on EMC, Boulder 1981 Used orbital welder on propellant tubing near electronics (Galileo spacecraft) Any voltage transient on pipe can couple into electronics “The basic welding process is benign” fuse blow test with welder measure energy to blow small fuse In this work, the risk for electronics came from V fluctuations on the pipe as the arc start circuit fired: 40 kV spark used to initiate arc Recommendations: Minimise starting power Ground tubing between weld and ESDS electronics Shield connectors Swagelok welder: output V ramps to 1600V before arc established - measured using potential divider and ‘ scope
Comparison with Literature - 2 * ESDS Equipment Susceptibility to Welding Generated EM Fields, Anderson et al, IEEE 1998 First principles calculation, welding on submarines Cables make current loop, associated B and E fields Arc radiates magnetic field (E small for scratch start) Changing magnetic fields induce voltage on PCB Recommendations: shield connectors, 15cm between welding and electronics Our numbers not frightening if we take 1/(converter f = 79 kHz ) as risetime (but watch out for start transient) ε ~ dϕ / dt
ESD testing of XCHIP Estimated energy: to melt diode 208 uJ to vapourise 1200uJ input showing ESD protection diodes IV curve input pad to GND before/after ESD test 2000V on 100pF = 200uJ HBM 2000V this region is gate leakage good gate => pA leakage damaged gate => nA leakage the protection diode has blown in the lower trace Thanks to Stephen Thomas (RAL)
How to blow an XSTRIP with the welder X XSTRIP input soldered directly to the pipe blows the input every time XSTRIP connected to pipe via ceramic C: damage scales with C, I should be possible to estimate actual C coupling to pipe (later) can we estimate a threshold for a given geometry and chip ? can we define a regime where we are confident of no damage ?? making the connection during the weld shows the channel blows as the arc starts, not during the weld itself
Effect of ground strap Repeat measurement New weld head May 2012 previously chip blew by 100pF, now 220pF weld head, temperature, humidity not the same.... not a big change for our purposes Chip 3 chan 11 with 1000pF After 9 welds 1 misfire Added ground strap – no damage Chip3 chan 13 with 470pF After 1 weld 40A/10A/10% No ground strap - blown
measurement of ABCN-25 before/after welding As feature size in CMOS process gets smaller, gate oxide gets thinner Detector ROIC: noise scales with input capacitance Trade-off between noise and ESD protection Input FET is the weakest point ABCN-25 has thinner gate oxide than XSTRIP BUT, standard IBM 250 um OK to HBM 4000V cf. XSTRIP HBM 2000V shown here 1 channel bonded to PCB at input C>Cdet One ABCN-25 channel has undergone a number of welds in proximity, no effect Also with channel connected to pipe (results on next slide !) Thanks to Peter Phillips
ABCN-25 after welding, test electrode bonded to input – capacitance causes excess noise
ABCN-25 after welding, bond pulled from input – gain, noise of tested channel normal
ABCN-25 I-V of input pad input connected to pipe 50A/5A/5% need to check for cumulative stress many welds followed by thermal ageing
ABCN-13 test chip destructive testing ABCN-13 front end test structure Calibration lines allow test pulse input 60 fF calibration capacitors ESD protection grounded gate NMOS Should protect for 1200V HBM Trade-off ESD protection vs noise Welding: one input bonded out SM capacitor on PCB Pipe placed in contact Very severe test ! Thanks to: Jan Kaplon, Matt Noy (CERN) Alexander Bitadze (Glasgow) Steve McMahon (RAL)
ABCN-13 destructive testing PCB10, 10pF cap, 40A/5A/10% A=102 σ=2.73 before A=101 σ=3.21 after ENC = (σ/A) * 15000 RMS e- => 399 initially, 476 finally
ABCN-13 destructive testing Compilation of all tests on 4 samples C = εA/W with V = eNDW2/2ε and ND=1E12 /cc strip is 2.5cm by 80μm depleted strip to backplane C = 0.7pF no bias strip to backplane C = 7pF ac coupling capacitor ~ 20pF welding OK, if coupling is small enough guesstimate coupling C ~ 5pF Need to measure it ! ground strap on pipe will improve matters a grounded layer in the bus tape ? ceramic breaks in the pipe (proposed for G+S) Sensor Bus tape Facing Foam core what is the equivalent circuit ?
FEI4 pixel chip destructive testing Tune the chip Save DAC settings Run with same settings + check Weld Run with same settings + check Tune: choose desired ToT for given Q in apply calibration pulses tune feedback and threshold DACs Check: threshold scan ToT verify analogue and digital tests Thanks to: Christian Gallrapp (CERN) Andy Blue, Kate Doonan, Richard Bates (Glasgow)
FEI4 pixel chip test results Threshold map from s-curve measured before/after a single weld Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons
FEI4 pixel chip test results Noise map from s-curve measured before/after a single weld Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons
FEI4 pixel chip test results ToT map for 10k electron cal pulses before/after a single weld Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons
Measurement of changing B-field Any loop can couple.... Use near field probes: http://www.ets-lindgren.com/7405 Work is ongoing Specific worry about DCDC coils Max. emf during start transient 3V measured with DCDC coil next to weld head 1V at realistic distance, orientation Grounded Al foil => x2 improvement Reproducibility suspect: T, humidity ?
Conclusions ROICs can be damaged by preamp input being capacitively coupled to voltage fluctuations on the pipe, as the arc is first initiated Fields near the weld head are not large and (with small statistics) no chip has ever failed by welding in proximity, without a deliberate input connection XSTRIP test structures: no damage until C way beyond a realistic setup. Damage preventable by ground strap between weld head and chip connection to pipe. ABCN-25: no damage for any setup tested so far ABCN-13: susceptible to damage at C which is “not unreasonable” FEI4: only tested by welding in proximity, no change Voltage induced on shielded DCDC inductor looks acceptable; best to discuss with DCDC experts
Where next ? Measuring the voltage fluctuations during welding and considering equivalent circuits could give a full understanding of the physics (maybe not necessary ?). Grounding, shielding and the welding programme could be tailored to prevent damage If ceramic breaks were added to the pipes, capacitive coupling will be minimal Could shielding be built in to stave ? Small mass cf. compression fittings.... Measure how a real module couples electrically to the pipe (simulation too ?) ? Further destructive tests with ABCN-13, more realistic test layout and ground strap Multiple welds followed by ageing at elevated T to check for latent damage Continue measurements with near field probes: coupling to loops, inductors
Measuring welder output current ‘scope traces with Current probe on output leads Low = 5A High = 10A 20% duty cycle Note >45A current spike at start Inverter f = 79 kHz Irrespective of current setting
Start voltage transient at welder output Arc start transient voltage few 10s of ms to fire Low = 5A High = 20A 10% duty cycle 200:1 potential divider => 1600 V Voltage during welding Low = 5A High = 40A 20% duty cycle 20:1 potential divider 10-20V
redefining the problem input FET ac-coupled detector arc We believe E and dB/dt from the arc likely to be too small to be relevant here. But we should demonstrate it (near field probes , module mockup, etc.?) ! to (over ?) simplify: pickup electrodes charge up a capacitance , which discharges into the input FET gate the geometry of the electrodes matters, relative to the electric field configuration the stored energy matters – need enough to rupture the gate, E = ½ CV2 the electrodes could couple capacitively to V fluctuations on the pipe The input FET is likely the most vulnerable point. All chip pads will have protection diodes, but big protection diodes decrease PSRR – so the diodes are made as small as possible. All open connectors would be grounded. bus cable
ESD protection in different technologies XCHIP ESD diodes 100 um * 100 um * 3 um HBM 2000V ABCN-25 standard library protection is HBM 4000V pdiode 495 p nwell diode 184 p actually used pdiode134 p, nwell diode 141 p, 15 Ohm HBM ?? < 4000V ABCN-13 standard library protection is HBM 4000V NFET 360 um / 240 nm actually used NFET 80um / 120nm – expect HBM 1200V
Measuring V on pipe Voltage on pipe relative to Wall ground High = 30A Low = 10A Duty cycle = 10% Upper: no deliberate pipe ground Lower: Cu braid grounding pipe Y- ground causes misfires ??
Where next ? equivalent circuits what are the relevant coupling capacitances ? what are the relevant arc sampling geometries ? the detector will be undepleted during welding ! can we scale between chip processes, based on gate parameters ?