Ayas Kanta Swain , Assistant Professor, ECE Dept ., NIT Rourkela

1. SystemVerilog Control Flow Ayas Kanta Swain, Assistant Professor, ECE Dept., NIT Rourkela

2. Control Flow

3. Loops • Loops execute over and over • A conditional statement included in the loops, so that it stops once the condition is met. • Loops running forever hangs Indefinitely.

4. Forever It runs for infinite time. It should have a delay element inside it.(Else Hang) In Classes “forever” block is used than “always”.

5. repeat • IT is used to repeat statements in a block for a certain no. of time.

6. while • It repeats a block as long as the condition is true.

7. do while • A do while executes the statements first and then checks for the condition to be true. If the condition is true then the statement are executed until the condition is false. Then loop ends.

8. for • It allows to mention the starting value, condition and incremental value. It repeats a given statement multiple times until the given expression is satisfied.

9. foreach • Arrays are data structures that stores many values in a single variable. • foreach is used to iterate over such array.

10. foreach • foreach is a shorter version of for

11. break

12. continue • c

13. If-else-if • If-else is used to check whether a statement is executed or not. SV uses the following if-else constructs for violation check. • unique-if • priority-if unique-if, unique0-if: unique-if evaluates the condition in parallel and does the following: • Report an error when none of the if conditions are true, or final if does not have an explicit else. • Report an error when there is more than 1 condition is true in if-else conditions.

19. priority-if priority-if evaluates all conditions in sequential order and a violation is reported when: none of the conditions are true or when final if does not have else clause

21. priority-if • a

22. unique case • SV case statements checks whether an expression matches one of a number of expressions and branches appropriately. (Same as Verilog) • It ensures there is no overlapping case items and hence can be evaluated in parallel. • If there are overlapping case items then violation is reported.

25. priority case

26. SystemVerilogEvent • Event is used to handle between two or more processes. • Once process triggers the event and another process waits for the event. How to trigger and wait for an event? • Namedevents can be triggeredusing->or->>operator • Processes can waitforaneventusing@operatoror.triggered

27. SystemVerilog Event

28. SytemVerilog Threads • What are SystemVerilog threads or processes ? • These are the separate entity that get executed separately. • A fork-join blocks creates a thread that run in parallel.

29. fork-join • Fork-join waits until all fork processes are completed.(blocking)

30. Fork-join_any • Fork-join_any waits until any one of the fork process is completed.(blocking)

31. fork-join_none • Fork-join_none does not wait and immediately exists the block allowing forked process running in the background. (non blocking)

33. Interface • Interface is an way to encapsulate signal into the block. • All related signals are grouped together to form block • Interface can be reused in other projects. • Easier to connect DUT and other verification components. • Logic is used as a type in interface. • Flexibility to use in procedural and concurrent blocks. • DUT signal must catch 4 –state values.(X/Z cannot be ignored)

34. Interface Declaring port direction. • Interface are used between various verification components and DUT. • modportis used to define signal direction. • Differentmodportcan be passed to different components that allows todefine different input output directions for each component.

35. Interface • Connecting interface to DUT: • It is created in the top testbench module where DUT is instantiated, and passed to DUT.(correct modport should be assigned to DUT).

36. Interface Advantage: • Interface may contains parameter, assertion, task and coverage etc. • It helps in monitoring and recording the transactions. • Easier to connect designs regardless of the number of ports • Parameterise an interface:

37. References • Chris Spear, “System Verilog for Verification: A Guide to Learning the Testbench Language Features”, Springer US, 2008 • Verificationexcellence. Usefedora.com • Chipverify.com • https://www.verificationguide.com/p/systemverilog-tutorial.html • http://www.asic-world.com/systemverilog/tutorial.html • http://www.testbench.in/SV_00_INDEX.html