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Selected Topics in VLSI Design

Selected Topics in VLSI Design. Results of Phase 1: First working FIR filter Design by Christoph Niemann and Vincent Wiese 30.10.2013. Institute MD, University of Rostock. Content. Adder Multiplier Architecture Implementation Metric Future Improvements. Adder. Ripple-Carry-Adder.

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Selected Topics in VLSI Design

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  1. Selected Topics in VLSI Design Results of Phase 1: First working FIR filter Design by Christoph Niemann and Vincent Wiese 30.10.2013 Institute MD, University of Rostock

  2. Content • Adder • Multiplier • Architecture • Implementation • Metric • Future Improvements

  3. Adder • Ripple-Carry-Adder Reference: Timmermann (2008): Script „Algorithmen der Datentechnik“ • small • easy toimplement • T = O(n) • A = O(n) • 40 bit data width for both summands and the sum

  4. Multiplier - Architecture • Shift-and-Add Multiplier • useof RCAs as CPAs • T = O(coeff_width*data_width) • A = O(coeff_width*data_width) Inspired by:: Timmermann (2008): Script „Algorithmen der Datentechnik“

  5. Multiplier - Implementation • Shift-and-Add Multiplier • uses 40-Bit unshifted RCAs • shiftoperationrealizedbyfilling in thedataintotherightpositionofthe 40-Bit summands • Extension fortwo‘scomplement • LSB‘sfilledupwith 0‘s • MSB‘sfilledupwitheither 1‘s or 0‘s depending on the MSB ofthedataword • last summandissubtracted

  6. Metric • Maximum Frequency: 53,378 MHz • Numberof Slice Registers: 762 • Numberof Slice LUTs: 5321 • Metric : 3,756*1016 [Hz³]

  7. Future Improvements • Direct Form II forthefilter • replacetheunshifted 40-bit adder in themultiplierbyshortershiftedones • evadeunnecessarrylongcriticalpathandwasteofchiparea • useof redundant adders • useof CSD-Recodingand Wallace-Trees in themultipliers

  8. Thank you for your attention!

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