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Selected Topics in VLSI-Design

Selected Topics in VLSI-Design. Robert Balla 4.Phase – Layout. Institute MD, University of Rostock. Overview. Improvements in VHDL Improvements in Synopsys Layout Timing Simulation Power Simulation Summary Frequency Response. Improvements in VHDL.

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Selected Topics in VLSI-Design

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  1. Selected Topics in VLSI-Design Robert Balla4.Phase – Layout Institute MD, University of Rostock

  2. Overview • Improvements in VHDL • Improvements in Synopsys • Layout • Timing Simulation • Power Simulation • Summary • Frequency Response

  3. Improvements in VHDL • Ignore less significant bits of Input and Output reduce number of registers smaller adders • Adjust filtercoefficients • Reduce number of multipliers • Registers between multipliers and adder

  4. Improvements in Synopsys • Use VHT-Libraries • „compileultra“

  5. Layout • Goal: short wiresreduce latencyreduce voltage drop • Parameters: • W = 67,451 um • H = 124,8 um • H/W ≈ 2 • Core utilization 90%

  6. Timing Simulation • Tmin = 0.95 ns  fmax ≈ 1053 MHz

  7. Power-Simulation • Positive Slack in Power-Simulation: 0,0269 ns  1083 MHz possible

  8. Frequency Response

  9. Summary

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