State Encoding of Large Asynchronous Controllers

1. State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain

2. Outline • Synthesis of Asynchronous Controllers (overview) • Structural approach for state encoding • Experimental results • Conclusions

3. This work Synthesis of Async. Controllers HDL CSP, Tangram, Balsa, Verilog… Graph Model Petri nets, Automata, … Logic Gates Complex gates, two-level, … Physical Implementation CMOS, FPGAs, …

4. y- y- a- a- a+ a+ b+ b+ x- x- y+ y+ b- b- x+ x+ y+ y+ c+ c+ x+ x+ y- y- x- x- c- c- Synthesis of Async. Controllers c synthesis a b y x Signal Transition Graph

5. Bus Data Transceiver DSr LDS Device D LDTACK DSr LDS VME Bus Controller DSw LDTACK D DTACK DTACK Read Cycle

6. read cycle write cycle DSr+ DSw+ DTACK- LDS+ D+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

7. D DTACK synthesis LDS DTACK- DSw+ csc DSr+ DSr LDS+ D+ LDTACK LDTACK+ LDS+ Implementation D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ D- DSw- Specification ?

8. D DTACK synthesis LDS DTACK- DSw+ csc DSr+ DSr LDS+ D+ LDTACK LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ 00000 01000 D- DSw- 10000 DSr+ DTACK- DSr+ DTACK- LDS+ LDS+ LDTACK- LDTACK- LDTACK- LDTACK- LDTACK- LDTACK- DSr+ DTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ LDS- LDS- LDS- LDTACK+ DSr+ DTACK- DSr+ DTACK- 10110 01110 10110 D+ D+ 11111 D- D- 10111 01111 DSr- DTACK+ DSr- DTACK+ State Graph (read cycle) Encoded State Graph

9. LDS+ LDTACK- LDS- LDTACK+ The encoding problem 00000 01000 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- 11111 10111 01111 DSr- DTACK+

10. D DTACK synthesis LDS DTACK- DSw+ csc DSr+ DSr LDS+ D+ LDTACK LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ 01000 D- DSw- csc + 10000 DSr+ DTACK- DSr+ DTACK- LDS+ LDS+ LDTACK- LDTACK- LDTACK- LDTACK- LDTACK- LDTACK- DSr+ DTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ LDS- LDS- LDS- LDTACK+ DSr+ DTACK- DSr+ DTACK- 10110 01110 10110 D+ D+ D- 11111 D- 10111 csc - 01111 DSr- DTACK+ DSr- DTACK+ Complete State Coding (CSC) EncodedState Graph

11. D DTACK synthesis LDS DTACK- DSw+ csc DSr+ DSr LDS+ D+ LDTACK Logic asynchronous circuit LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ D- DSw- csc + DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- csc - DSr- DTACK+ Complete State Coding (CSC) Boolean equations: LDS = D  csc DTACK = D D = LDTACK csc = DSr

12. DTACK- DSw+ DSr+ LDS+ D+ LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ D- DSw- DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DSr- DTACK+ State Graph State space explosion problem

13. Event-based vs. State-based model State Graph Petri Net

14. DTACK- DSw+ DSr+ DSr+ DTACK- LDS+ D+ LDTACK+ LDS+ LDS+ LDTACK- LDTACK- D+ LDTACK- LDTACK+ DSr+ DTACK- D- DTACK+ LDS- DSr- DTACK+ LDS- LDS- LDS- LDTACK+ D- DSw- DSr+ DTACK- csc + DSr+ DTACK- D+ LDS+ LDTACK- LDTACK- LDTACK- D- DSr+ DTACK- DSr+ DSw+ DSr- DTACK+ DTACK- csc+ csc+ LDS- LDS- LDS- LDTACK+ LDS+ D+ DSr+ DTACK- LDTACK+ LDS+ LDTACK- D+ D+ LDTACK+ D- LDS- D- DTACK+ csc- csc - DSr- DTACK+ DSr- DTACK+ D- DSw- Our approach to state encoding

15. Outline • Synthesis of Asynchronous Controllers (overview) • Structural approach for state encoding: • Detection of conflicting states • Disambiguation by consistent signal insertion • Main algorithm for conflict resolution • MILP model to insert consistent signals • Experimental results • Conclusions

16. DTACK- DSw+ DSr+ LDS+ D+ LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ D- DSw- Detection of conflicting states LDS+ LDTACK- LDS- LDTACK+ DSr+ DTACK- D+ D- DSr- DTACK+ • ILP • [Carmona & Cortadella, ICCAD’03] • SAT-UNFOLD • [Khomenko et al., Fund. Informaticae]

17. DTACK- DSw+ DSr+ LDS+ D+ LDTACK+ LDS+ D+ LDTACK- LDTACK+ D- DTACK+ LDS- DSr- DTACK+ D- DSw- s+ s- Disambiguation by consistent signal insertion Disambiguate the conflicting states by introducing a new signal s: • STG Insertion of signal s must: • Solve conflict • Preserve consistency • Preserve persistency 10000 (CSC + consistency + persistency = SI-circuit) LDS+ LDTACK- 10100 10010 LDS- LDTACK+ 01110 DSr+ DTACK- 10110 10110 D+ D- 11111 10111 DSr- DTACK+ 01111

18. Implicit place DEF1 (Behavior): The behavior of the net does not depend on the place. DEF2 (Petri net): it never disables the firing of a transition. y+ b+ a+ a- b- x+ y- x- x- b- y- a- a+ x+ x+ y+ b+ y-

19. y+ x- y- b+ x- x+ b- y+ ... y+ x- y- b+ x- x+ b- y+ ... ? Consistency Consecutive firings of a signal must alternate b+ y- y+ x- y- b+ x- x+ b- y+ ... x+ x- x- b- y+

20. y=0 y=1 Implicit Places & Consistency b+ y- x+ x- x- b- y+ Theorem (Colom et al.) Places y=0 and y=1 are implicitif and only if signal y is consistent

21. s- s+ Disambiguation by consistent signal insertion Disambiguate the conflicting states by introducing a new signal s: • Insertion of s into the STG: • s- will precede LDS+ • s+ will precede DTACK- LDS+ LDTACK- s- ; LDS+ LDS+ LDS- LDTACK+ DSr+ DTACK- D+ D- DSr- DTACK+

22. s=0 s=1 read cycle write cycle DSr+ DSw+ DTACK- s+;DTACK- LDS+ s-;LDS+ D+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

23. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

24. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

25. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

26. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

27. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

28. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

29. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ s=0 is not implicit!! LDTACK+ LDS+ s is not consistent!! s=0 s=1 LDTACK- D+ LDTACK+ DTACK+ D- LDS- DSr- DTACK+ D- DSw-

30. read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ s=0is implicit s=1is implicit LDTACK+ LDS+ s=0 s=1 LDTACK- D+ LDTACK+ s is consistent DTACK+ s-;D- D- LDS- DSr- DTACK+ D- DSw-

31. s=0 s=1 read cycle write cycle DSr+ DSw+ s+;DTACK- s-;LDS+ D+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ DTACK+ s-;D- LDS- DSr- DTACK+ D- DSw-

32. read cycle write cycle s+ DSr+ DSw+ DTACK- s- D+ LDS+ LDTACK+ LDS+ LDTACK- D+ LDTACK+ s- DTACK+ D- LDS- DSr- DTACK+ D- DSw-

33. Main algorithm for solving CSC conflicts while CSC conflits exist do (σ1,σ2):= Find traces connecting conflict (s=0,s=1):= Find implicit places to break conflict Insert s+/s- transitions connected to (s=0) or (s=1) endwhile

34. State space explosion problem • Goal: avoid state enumeration to check implicitness of a place. • Classical methods to avoid the explicit state space enumeration: • Linear Algebra (LP/MILP) • Graph Theory • Symbolic representation (BDDs) • Partiar order (Unfoldings) Structural methods

35. a+ c+ a+ a- b+ b+ b- c+ c- p1 -1 0 0 0 1 -1 0 p2 1 0 -1 0 0 0 0 p3 1 -1 0 0 0 0 0 p4 0 0 0 0 0 1 -1 p5 0 0 0 -1 0 1 0 p6 0 0 1 0 -1 0 1 p7 0 1 0 1 -1 0 0 b+ a- c- b+ b- Marking equation p1 Incidence matrix p3 p4 p2 p5 p6 p7

36. 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0 Marking equation M’ = M + Ax p1 p2 p3 p4 p5 p6 p7 = + Necessary reachability condition, but not sufficient.

37. LP model to check place implicitness A place p is implicit if the following LP model is infeasible,where P’ = P – {p}: x M0 M LP formulation: M0 + Ax = M M[P’] – F[P’,p•]·s 0 M[p] – F[p,p•]·s <0 s·1 = 1 x, M, s  0 P – {p}: p . . . M : [Silva et al.]

38. LP model to check place implicitness A place p is implicit if M0[p] is greater than or equal to the optimal value of the following LP, where P’ = P – {p}: A place p is implicit if the following LP model is infeasible,where P’ = P – {p}: DUAL LP formulation: M0 + Ax = M M[P’] – F[P’,p•]·s 0 M[p] – F[p,p•]·s <0 s·1 = 1 x, M, s  0 LP formulation: min y· M0 y·A[P’.T] ≤ A[p,T] y· F[P’, p•] ≥ F[p, p•] y≥ 0 [Silva et al.]

39. MILP model to insert a implicit place MILP formulation: min y· M0 y·A’[P’.T] ≤ A’[p,T] y· F’[P’, p•] ≥ F[p, p•] y≥ 0 A A’ p MILP variables: y, p

40. MILP model to find insertion points that disambiguate the conflict MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #(σ1,s+) = #(σ1,s-) + 1 #(σ2,s-) = #(σ2,s+) + 1 M0[s=0] + M0[s=1] = 1 LDS+ LDTACK- σ1 σ2 LDS- LDTACK+ DSr+ DTACK- D+ D- If there is a solution, rows in A’ for s=0 and s=1 describe the insertion points (arcs in the net) DSr- DTACK+

41. Outline • Synthesis of Asynchronous Controllers (overview) • Structural approach for state encoding • Experimental results • Conclusions

42. petrify (state-based) MILP (structural) Number of inserted encoding signals Benchmarks from [Cortadella et al., IEEE TCAD’97]

43. petrify (state-based) MILP (structural) Number of literals (area) Benchmarks from [Cortadella et al., IEEE TCAD’97]

44. Experimental results: large controllers Synthesis with structural methods from [Carmona & Cortadella, ICCAD’03]

45. It doesn’t always work ... Behaviorally equivalent

46. Conclusions • First structural approach to state encodingfor general STGs. • Solutions comparable to state-based methods. • Structural approach  can handle large controllers (few thousands of signals). • May benefit from the well-structured specs obtained from HDLs.