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7-Segment Display

7-Segment Display. DIO1 Board Verilog. Digilab2 – DIO1 Boards. Four 7-segment displays. A0. A1. A2. A3. DIO1 Board – Common Anodes. Pins. A0 A1 A2 A3. Pins. AtoG(6:0). Multiplex displays. 0. 0. 0. 1. 0 0 0 0 1 1 0. Multiplex displays. 0. 0. 1. 0.

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7-Segment Display

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  1. 7-Segment Display DIO1 Board Verilog

  2. Digilab2 – DIO1 Boards Four 7-segment displays A0 A1 A2 A3

  3. DIO1 Board – Common Anodes Pins A0A1 A2 A3 Pins AtoG(6:0)

  4. Multiplex displays 0 0 0 1 0 0 0 0 1 1 0

  5. Multiplex displays 0 0 1 0 0 0 0 1 1 1 1

  6. Multiplex displays 0 1 0 0 1 0 0 1 1 0 0

  7. Multiplex displays 1 0 0 0 0 1 1 1 0 0 0

  8. x7seg

  9. x7seg.v module x7seg(x,cclk,clr,AtoG,A); input [15:0] x; input cclk, clr; output [6:0] AtoG; output [3:0] A; reg [6:0] AtoG; reg [3:0] A; integer k; reg [3:0] digit; reg [1:0] count;

  10. // ctr2bit always @(posedge cclk orposedge clr) if(clr) count <= 0; else count <= count + 1;

  11. // Mux4 always @(x,count) case(count) 0: digit = x[15:12]; 1: digit = x[11:8]; 2: digit = x[7:4]; 3: digit = x[3:0]; default: digit = x[3:0]; endcase

  12. // seg7dec always @(digit) case(digit) 0: AtoG = 7'b0000001; 1: AtoG = 7'b1001111; 2: AtoG = 7'b0010010; 3: AtoG = 7'b0000110; 4: AtoG = 7'b1001100; 5: AtoG = 7'b0100100; 6: AtoG = 7'b0100000; 7: AtoG = 7'b0001111; 8: AtoG = 7'b0000000; 9: AtoG = 7'b0000100; 'hA: AtoG = 7'b0001000; 'hb: AtoG = 7'b1100000; 'hC: AtoG = 7'b0110001; 'hd: AtoG = 7'b1000010; 'hE: AtoG = 7'b0110000; 'hF: AtoG = 7'b0111000; default: AtoG = 7'b0000001; // 0 endcase

  13. // Acode always @(count) for(k = 0; k <= 3; k = k+1) if(count == k) A[k] = 1; else A[k] = 0; endmodule Example: count = 10 A[2] = 1 A[0] = A[1] = A[3] = 0 A[3:0] = 0100

  14. x7seg_test.v module x7seg_test(mclk,bn,led,ldg,SW,AtoG,A); input [1:8] SW; input mclk, bn; output ldg, led; output [6:0] AtoG; output [3:0] A; wire [6:0] AtoG; wire [3:0] A; wire clr, cclk, bnbuf; reg [23:0] clkdiv; wire [7:0] fix;

  15. IBUFG U00 (.I (bn), .O (bnbuf)); assign led = bnbuf; assign clr = bnbuf; assign ldg = 1; // enable 74HC373 latch // Divide the master clock (50Mhz) always @(posedge mclk) begin clkdiv <= clkdiv + 1; end assign cclk = clkdiv[17]; // 190 Hz assign fix = 8'b10100101; x7seg U1(.x({fix,SW}),.cclk(cclk),.clr(clr),.AtoG(AtoG),.A(A)); endmodule

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