Dual Core System-on-Chip Design to Support Inter-Satellite Communications

1. Dual Core System-on-Chip Design to Support Inter-Satellite Communications EEL 6935 - Embedded Systems Dept. of Electrical and Computer Engineering University of Florida Liza Rodriguez Aurelio Morales

2. Outline • Introduction • Picosatellite Demostrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

3. Outline • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

4. Introduction Distributed Satellite System (DSS) • Satellites that provide multi-point sensing • Low cost, redundancy, flexibility • Types of DSS: • Formation Flying: strict formation • Clustering Mission: satellites are loosely coupled around each other • Virtual Satellite Mission (fractioned mission): a satellite has its subsystems divided onto multiple crafts (computing, imaging, etc.)

5. Introduction DSS in Low Earth Orbit (LEO) • Small satellites deployed at the same time in multiple orbits • Use for disaster monitoring prevention • Ad-hoc network for multipoint sensing like WSN • Challenges: • Attitude and orbit control, intersatellite links, on-board computing • Deal with perturbations: Earth’s geophysical forces, solar radiation • Network connectivity and topology over time

6. Introduction Distributed Computing Requirements • Node Level • At Individual satellite level • Store and forward data using the network: • High priority apps using Client/Server. Payload data through the network such imaging data • Low priority apps using Peer-to-Peer telemetry. Location and velocity changes, “byte” size payload data (GPS) • Network Level • Applied to multiple satellites • Provide adaptable and redundant ground-link communication schemes, main “sink” to ground • React proactively and reactively to their environment

7. Motivation • Meet requirements for processing and network capabilities in “cluster” of satellites in the presence of space disturbances Proposal • Dual core System-on-Chip design using a general purpose soft-core processor and a specific core for real-time applications, such as agents Introduction

8. Agenda • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

9. Picosatellite Demonstrator Design Prototype • Use of embedded hardware technology • Standard picosatellite platform CubeSat • For fast prototype, COTS components/boards: • Flight OBC and satellite chassis from Pumpkin • Power module from Clyde-Space • SGR-05 GPS module from SSTL • MHX transceiver from Microhard Systems • PF5100 Virtex-4 FPGA FX60 Board for SoC • IEEE 802.11 PC/104 Board from Elcard

10. CubeSat Platform with Flight Module, IEEE 802.11, FPGA and development boards Prototype

11. Power Module SGR-05U – Space GPS Receiver Flight module and satellite Chassis MHX 900 MHz Transceiver PF5100 Board with Virtex-4 FPGA IEEE 802.11 Board Prototype

12. 1999, CalPoly and Stanford University developed specs to help universities worldwide perform space exploration. • Very small satellite • Use COTS components • 10x10x10 cm structure • Weight of 1 Kg • Also in 2U and 3U sizes CubeSat

13. Demonstrator Satellite Architecture • FPGA board, IEEE 802.11 board, camera as payloads. • Architecture controlled by the Flight On-Board Computer (FM430 OBC) • SoC to act as HW/SW mediator for: • Hard and soft resets • Sleep mode • SoC also used as interface between various buses Demonstrator Satellite Architecture

14. Agenda • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

15. LEON3 Processor • Synthesisable VHDL model of 32-bit processor compliant with SPARC V8 architecture • Suitable for SoC designs JOP Processor • Java Optimized Processor • Enables real-time Java functionality • Smallest and fastest Java core Dual Core Processor Design

16. Dual Core Processor Design LEON3 Processor

17. Dual Core Processor Design FPGA SoC design LEON3 core and JOP core in a FPGA AMBA = Advanced Microcontroller Bus Architecture APB = Advanced Peripheral Bus

18. Dual Core Processor Design Design Considerations • Memory sharing system between LEON3 and JOP for access to external RAM • Cache between cores must maintain coherency • Reconfiguration in cases of single event upsets (SEUs) or single event latch-ups (SELs)

19. Memory Footprint Comparison • System must have low memory footprint, including OS and network stack • System must be real-time • CLDC and pjava are designed for devices with intermittent network connection, slow processors, limited memory (e.g. mobile phones, PDAs), making them ideal for JOP core CLDC = Connection Limited Device Configuration pjava = PersonalJava JADE= Java Agent DEvelopment Framework LEAP =Light Extensible Agent Platform CORBA = Common Object RequestBroker Architecture Dual Core Processor Design Multi-layer software design

20. Dual Core Processor Design Hardware and software layer design LEON3 and JOP in FPGA: • Reduce memory footprint • Increase FPGA utilization • Enable Java apps, such as Agents, for real-time apps RTEMS = Real-Time Exceutive for Multiprocessor Systems

21. System-on-Chip Block Diagram Dual Core Processor Design Detailed System-on-Chip design

22. Outline • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

23. Dual Core Processor Implementation Timing Results • Max Frequency of 37.398 MHz • WCET found between: • LEON3 and AMBA memory controller • LEON3 and JOP AHB Master • JOP cache and JOP address bus • Speed optimization is needed to satisfy IEEE 802.11 MAC. Trade-off between area and speed

24. Resource Utilization Memory Trade-off • On-chip or off-chip memory? • Speed and power requirements • On-chip: fast but increase power consumption and area • Power consumption of SoC design: 2.33W (1.76W in memory interfacing), using XPower from Xilinx Dual Core Processor Implementation

25. Outline • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

26. HW & SW are discovered • Network topology can be reconfigured Network Topology Reconfiguration Procedure • Stage 1: Startup FPGA Bus System & LEON3 • LEON3 started, id and starting tasks discovered • Stage 2: Startup JOP & JADE-LEAP • Start Java application with argument passing to main host and services required • Stage 3: Network Topology Refresh • Initialize, check or change the network topology

27. Outline • Introduction • Picosatellite Demonstrator Design • Dual Core Processor Design • Dual Core Processor Implementation • Network Topology Reconfiguration • Conclusions

28. Conclusions • A COTS solution for picosatellite including a SoC design that meets CubeSat platform was introduced. • LEON3 IP and JOP IP cores were used to meet strict requirement of low memory footprint, Java functionality and real-time operation • An Java agent software was proposed to support inter-satellite communication based on IEEE 802.11 wireless connectivity

29. References • http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273 • http://www.cubesat.org/ • http://en.wikipedia.org/wiki/CubeSat • http://www.cubesatkit.com/index.html • http://www.derivation.com/products/pf5100.html • http://www.clyde-space.com/products/electrical_power_systems/cubesat_power • http://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdf • http://www.data-connect.com/Microhard_MHX-910.htm • http://www.gaisler.com/doc/leon3_product_sheet.pdf

30. Questions?