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Noise Canceling in 1-D Data: Presentation #4

Feb 14 th , 2005 Gate Level Design. Noise Canceling in 1-D Data: Presentation #4. Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar. M2. Project Manager: Bobby Colyer. Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware.

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Noise Canceling in 1-D Data: Presentation #4

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  1. Feb 14th, 2005 Gate Level Design Noise Canceling in 1-D Data: Presentation #4 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Project Manager: Bobby Colyer Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

  2. Status • Design proposal (Done) • Architecture proposal (Done) • Size Estimates and Floorplan: • Structural Verilog (Done) • Revised Floorplan (Done) • To be done: • Schematics (85%) • Layout (5%) • Spice simulation

  3. Previous Block Diagram

  4. Final Block Diagram

  5. Structural Verilog Output Behavioral Verilog Output Structural Verilog Output Similar Output Values. Differences due to 16-bit Floating Point Units

  6. Result Comparison

  7. New Transistor Count…

  8. Area Estimates

  9. Revised Floorplan

  10. Mux 16-bit 2:1 Layout

  11. Schematics

  12. ROM

  13. Alignment Shifter

  14. Leading Zero Counter

  15. Rounding Unit

  16. Normalizing Unit

  17. Wallace Tree Multiplier

  18. Input of ROM Table Testbench

  19. Test Results for Sine Time = 40ns Input: 2.52 (21st value) SinOutput: 00110001 = 0.5823

  20. Test Results for Cosine Time = 40ns Input: 010100 (21st value) CosOutput: 10110101 = -0.8130

  21. Critical Path Estimation • Cycle 2 will be longer than Cycle 1 because it uses 3 FPM + 2 FPA while Cycle 1 uses 2 FPM + 3 FPA

  22. Last week’s challenges… • Finalizing out designs for the floating point adders and multipliers • Wallace tree multiplier vs Array multiplier • Choose Wallace implementation because it saves 10% of power • Leading zero counter for normalizing block • Found a smaller implementation of the normalizing block

  23. This week’s challenges… • Completing and Testing Top level Schematic • Creating Layouts for Floating Point Multipliers and Adders with different shapes • Clock Skew and other Timing issues • Transistor count .. again..

  24. Questions?

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