COMBINATIONAL LOGIC DESIGN PRACTICES

1. COMBINATIONAL LOGIC DESIGN PRACTICES

2. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

3. DOCUMENTATION • WHAT? • SPECIFICATION: INTERFACE, FUNCTION • HOW? • BLOCK DIAGRAM • SCHEMATIC DIAGRAM • TIMING DIAGRAM • STRUCTURED LOGIC DEVICE DESCRIPTION • CIRCUIT DESCRIPTION

4. BLOCK DIAGRAMS • INPUTS, OUTPUTS • FUNCTIONAL MODULES • DATA PATHS • CONTROL SIGNALS

5. BLOCK DIAGRAMS

6. BUS • COLLECTION OF TWO OR MORE RELATED SIGNALS • SLASH AND NUMBER: NUMBER OF SIGNALS

7. SIGNAL NAMES • WELL CHOSEN NAMES CONVEY INFORMATION

8. SIGNAL ACTIVE LEVELS • ACTIVE HIGH • ACTIVE LOW • ASSERTED WHEN AT THE ACTIVE LEVEL • DEASSERTED (NEGATED) WHEN NOT AT THE ACTIVE LEVEL

9. NAMING CONVENTION • ACTIVE HIGH: GO, PAUSE, READY • ACTIVE LOW: GO~, PAUSE.L, /READY, ETC.

10. ACTIVE LEVELS FOR PINS • INVERSION BUBBLE: ACTIVE LOW • NO INVERSION BUBBLE: ACTIVE HIGH

11. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

12. CIRCUIT TIMING • TIMING DIAGRAM • RELATIONSHIPS AMONG INTERNAL SIGNALS • REQUIREMENTS ON EXTERNAL SIGNALS • CAUSALITY • DELAY  TIMING TABLE • DELAYS  RANGE: MINIMUM, MAXIMUM, TYPICAL • PROPAGATION DELAY (tHL, tLH,…)

13. TIMING SPECIFICATIONS • MAXIMUM: HOW DID THEY MEASURE IT? • TEMPERATURE (25 °C, 40 °C, …) • CAPACITIVE LOAD (0 pF, 50 pF, …) • VCC (3.3V, 5V, …) • TYPICAL • IDEAL? • MINIMUM • WORK FOR ZERO DELAY? • TEMPERATURE, LOAD, VCC, …

14. TIMING ANALYSIS • COMPLEX FOR LARGE CIRCUITS • CAD TOOLS HELP, BUT: • NEED TO UNDERSTAND WHAT THE RESULTS ARE • OFTEN MANY CONTROLS  NEED TO KNOW HOW TO TEST

15. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

16. DECODERS • MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS • INPUT AND OUTPUT CODES ARE DIFFERENT • ONE-TO-ONE MAPPING

17. DECODERS

18. BINARY DECODERS • n-TO-2n DECODERS • ACTIVATE EXACTLY ONE OF 2n OUTPUTS BASED ON n-BIT INPUTS

19. 2-TO-4 BINARY DECODER

20. LOGIC SYMBOLS

21. ONE-HALF OF 74x139 DECODER

22. ONE-HALF OF 74x139 DECODER

23. 74x138 3-TO-8 DECODER

24. CASCADING BINARY DECODERS • 74x138 HAS BOTH ACTIVE HIGH AND ACTIVE LOW ENABLE INPUTS • WITH TWO 138s WE CAN ENABLE OR THE OTHER USING THE MSB

25. SEVEN-SEGMENT DECODER

26. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

27. ENCODERS • MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS • OUTPUT CODE HAS FEWER BITS • ONE-TO-ONE MAPPING

28. BINARY ENCODER • 2n-TO-n ENCODER • INPUT: 1-OUT-OF-2n CODE • OUTPUT: n-BIT BINARY CODE

29. BINARY ENCODER

30. BINARY ENCODER Y0=I1+I3+I5+I7 Y1=I2+I3+I6+I7 Y2=I4+I5+I6+I7

31. PRIORITY ENCODERS

32. 8-INPUT PRIORITY ENCODER

33. 74x148 PRIORITY ENCODER

34. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

35. THREE-STATE DEVICES • ENABLE - DEVICE “FLOATS” • FLOATS = HIGH IMPEDANCE STATE = = HI-Z STATE = DISCONNECTED STATE

36. MULTIPLE SOURCES ON THREE-STATE PARTY LINE • MULTIPLE THREE-STATE DEVICES CAN SHARE SINGLE LINE • FIGHTING • DEAD TIME

37. MULTIPLE SOURCES ON THREE-STATE PARTY LINE

38. STANDARD THREE-STATE BUFFERS • HYSTERESIS? • BUFFERS • TRANSCEIVERS

39. COMBINATIONAL LOGIC DESIGN PRACTICES • DOCUMENTATION • TIMING • DECODERS • ENCODERS • THREE-STATE DEVICES • MULTIPLEXERS • XOR GATES AND PARITY CIRCUITS • COMPARATORS

40. MULTIPLEXERS • DIGITAL SWITCH

41. MULTIPLEXERS

42. 74x151, 74x157

43. 74x153

44. THREE-STATE MUXES • DISABLED OUTPUT HI-Z INSTEAD OF 0: • 74x151  74x251 • 74x153  74x253 • 74x157  74x257

45. EXPANDING MUXES • EXPAND THE NUMBER OF BITS  MULTIPLE 74x151s… • FANOUT • EXPAND THE NUMBER OF SOURCES

46. MUXES, DEMUXES, BUSES

47. MUXES, DEMUXES, BUSES

48. DECODERS AS DEMUXES

49. DECODERS AS DEMUXES

50. DESIGN EXAMPLE • CREATE A MUX-DEMUX SYSTEM FOR A 2-BIT BUS • 4 2-BIT INPUTS TO 4 2-BIT OUTPUTS • USE STANDARD TTL CHIPS FROM BOOK