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Combinational Logic Design: Adder

Combinational Logic Design: Adder. Overview. Binary Addition Half Adder Full Adder Ripple Carry Adder Carry Lookahead Adder Decimal Addition (Section 3.12) BCD Adder. Chapter 3-iv: Combinational Logic Design (3.8). 2. Oct-22-10. 1-bit Adder. Performs the addition of two binary bits.

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Combinational Logic Design: Adder

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  1. Combinational Logic Design: Adder

  2. Overview • Binary Addition • Half Adder • Full Adder • Ripple Carry Adder • Carry Lookahead Adder • Decimal Addition (Section 3.12) • BCD Adder Chapter 3-iv: Combinational Logic Design (3.8) 2 Oct-22-10

  3. 1-bit Adder • Performs the addition of two binary bits. • Four possible operations: • 0+0=0 • 0+1=1 • 1+0=1 • 1+1=10 • Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry. Chapter 3-iv: Combinational Logic Design (3.8) 3 Oct-22-10

  4. Half Adder • Performs 1-bit addition. • Inputs: A0, B0 • Outputs: S0, C1 • Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. • Boolean equations: • S0 = A0B0’+A0’B0 = A0⊕ B0 • C1 = A0B0 Truth Table Chapter 3-iv: Combinational Logic Design (3.8) 4 Oct-22-10

  5. Half Adder (cont.) • S0 = A0B0’+A0’B0 = A0⊕ B0 • C1 = A0B0 Block Diagram Logic Diagram B0 A0 A0 S0 1 bit half adder B0 C1 C1 S0 Chapter 3-iv: Combinational Logic Design (3.8) 5 Oct-22-10

  6. n-bit Addition • Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. • Example: Let n=4Cout C3 C2 C1 C01 1 0 1 0 A3 A2 A1 A0 1 1 0 1 +B3 B2 B1 B0 +1 1 0 1 -------------- ---------- S3 S2 S1 S0 1 0 1 0 • This requires 3-bit addition! Chapter 3-iv: Combinational Logic Design (3.8) 6 Oct-22-10

  7. Full Adder • Full adder (for higher-order bit addition) • Combinational circuit that performs the additions of 3 bits (two bits and a carry-in bit) Ai Bi 1 bit full adder Ci+1 Ci Si Chapter 3-iv: Combinational Logic Design (3.8) 7 Oct-22-10

  8. Full Adder (cont.) The K-maps for Ci+1: Si: BiCi Ai 0 0 1 0 0 1 1 1 BiCi Ai 0 1 0 1 1 0 1 0 Chapter 3-iv: Combinational Logic Design (3.8) 8 Oct-22-10

  9. Full Adder (cont.) • Boolean equations: • Ci+1 = AiBi + AiCi + BiCi • Si = AiBi’ Ci’ + Ai’Bi’Ci + Ai’BiCi’ + AiBiCi = Ai⊕ Bi⊕ Ci • You can design full adder circuit directly from the above equations (requires 3 ANDs and 1 OR for Ci+1 and 2 XORs for Si) • Can we do better? Chapter 3-iv: Combinational Logic Design (3.8) 9 Oct-22-10

  10. Full Adder using 2 Half Adders A full adder can also be realized with two half adders and an OR gate, since Ci+1 can also be expressed as: Ci+1 = AiBi + AiBi’Ci + Ai’BiCi = AiBi + (AiBi’ + Ai’Bi)Ci = AiBi + (Ai ⊕ Bi)Ci and Si = Ai⊕ Bi⊕ Ci Ai Si Bi Ci+1 Ci Chapter 3-iv: Combinational Logic Design (3.8) 10 Oct-22-10

  11. n-bit Combinational Adders • Perform parallel multi-bit addition • Ripple Carry Adder • Simple design • Time consuming. Why? (you’ll see in a bit!) • Carry Lookahead Adder • More complex than ripple-carry adder • Reduces circuit delay Chapter 3-iv: Combinational Logic Design (3.8) 11 Oct-22-10

  12. n-bit Ripple Carry Adder • Constructed using n 1-bit full adder blocks in parallel. • Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position. Chapter 3-iv: Combinational Logic Design (3.8) 12 Oct-22-10

  13. Example: 4-bit Ripple Carry Adder C4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------- S3 S2 S1 S0 Chapter 3-iv: Combinational Logic Design (3.8) 13 Oct-22-10

  14. Ripple Carry Adder Delay • Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C0) to the MSB (Cn). • Let the delay in a 1-bit FA be Δ. Then, the delay of an n-bit ripple carry adder is nΔ. Chapter 3-iv: Combinational Logic Design (3.8) 14 Oct-22-10

  15. Carry Lookahead Adder • Alternative design for a combinational n-bit adder. • Practical design with reduced delay at the expense of more complex hardware. • See Wakerly 5.10.4 Chapter 3-iv: Combinational Logic Design (3.8) 15 Oct-22-10

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