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Software Engineering Methodology for Reconfigurable Platforms

Software Engineering Methodology for Reconfigurable Platforms. Damien Picard and Loic Lagadec Architectures et Systèmes, Lab-STICC Université de Bretagne Occidentale, France ESUG’09 Brest, France, 2009. Introduction. Increasing complexity of modern System-on-Chip

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Software Engineering Methodology for Reconfigurable Platforms

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  1. Software Engineering Methodology for Reconfigurable Platforms Damien Picard and Loic Lagadec Architectures et Systèmes, Lab-STICC Université de Bretagne Occidentale, France ESUG’09 Brest, France, 2009

  2. Introduction • Increasing complexity of modern System-on-Chip • Difficulty to program and to validate applications • Shrinking time-to-market • Common techniques for hardware validation • Testing/debugging at a very low abstraction level  Time-consuming and burdensome • Need for productive methodologies with an higher level approach • Software development benefits from very efficient techniques • Our approach: applying software engineering methodologies to hardware design

  3. Aim of this talk • This talk focuses on a key issue: validation of hardware application targeting RA • An HL synthesis flow for reconfigurable architectures based on MADEO [ESUG 08] • Multi-level simulation: from behavioral to hardware • Interfacing with third-party tools through code generation • Software-like debugging features embedded in hardware • Advocates for the use of software engineering techniques • Short development cycles, use of OO models, code generation, etc.

  4. Outline • Overview of Reconfigurable Architectures • OO methodology for synthesis on RA • Simulation and testing methodology • Software-like debugging for RA • Conclusion

  5. Outline • Overview of Reconfigurable Architectures • OO methodology for synthesis on RA • Simulation and testing methodology • Software-like debugging for RA • Conclusion

  6. Reconfigurable Architectures • A reconfigurable architecture is a run-time programmable architecture based on the hardware reconfiguration • Used as flexible hardware accelerators for intensive computations • Based on Look-Up-Table (LUT) = memory • General-purpose and high parallelism • Slow and area/power-inefficient (routing overhead) • Several reconfigurable platforms • FPGAs (vendors, e.g. Xilinx, Altera) • eFPGAs (e.g. M2000, Menta) • RSoCs (e.g. Morpheus project): RA IP composition

  7. Reconfigurable Architectures • Trade-off between flexibility/performance • Functionality of the circuit determined by a configuration Program Data Configuration Data Data Processor Reconfigurable Architecture ASIC Results Results Results Flexibility Performance

  8. Reconfigurable Architectures • FPGA: a general overview • Organized as a mesh of look-up-tables • Possibly heterogeneous + * - Computing resource i1 µP LUT LUT I1-i2 IO LUT i2 LUT i1 i1 LUT LUT I1*i2 I1+i2 i2 i2 Programmable interconnection LUT LUT LUT

  9. Outline • Overview of Reconfigurable Architectures • OO methodology for synthesis on RA • Simulation and testing methodology • Software-like debugging for RA • Conclusion

  10. The MADEO framework • Loic Lagadec’s talk: “MADEO: A CAD Tool for Reconfigurable Hardware” [ESUG 08] • MADEO is a generic synthesis framework for RA • Set of open tools designed with OO principles for fast evolution • Enables design-space exploration • Application of OO methodology for synthesizing circuits • Flexibility through generic OO model with a common API • Adapt to new RA “retargetable compiler” • Produce circuits from HL pure OO code: Smalltalk

  11. Madeo: Global Flow Application Target Architecture Description Smalltalk Method Instantiation Abstract Model Madeo Synthesis Tools Netlist Concrete Architecture Place&Route Configuration (bitstream)

  12. A complete implementation sad4p1: p1 p2: p2 | sub0a sub1a sub0b sub1b sub0 sub1 cond0 cond1 p10 p11 p20 p21 | p10 := p1. p11 := p1 bitShift: 8. p20 := p2. p21 := p2 bitShift: 8. sub0a := p10-p20. sub0b := p20-p10. cond0 := sub0a<0. sub0 := cond0 ifTrue:[sub0b] ifFalse:[sub0a]. sub1a := p11-p21. sub1b := p21-p11. cond1 := sub1a<0. sub1 := cond1 ifTrue:[sub1b] ifFalse:[sub1a]. ^sub0+sub1.

  13. The MADEO framework • Software-engineering concepts applied to logic synthesis on reconfigurable architectures • MADEO: extensive use of OO methodology • Modeling, generic tools through polymorphism • An HL synthesis flow for RSoC based on the MADEO approach with validation methodology • Multi-level simulation: from behavioral to hardware • Target modeling • Interfacing with third-party tools through code generation • Software-like debugging features embedded in hardware

  14. Outline • Overview of Reconfigurable Architectures • OO methodology for synthesis on RA • Simulation and testing methodology • Software-like debugging for RA • Conclusion

  15. Global Flow Smalltalk Method Components Framework CDFG High-level CDFG SoC Model Synthesis Low-level CDFG System Simulator Multi-Level Simulator Testing Export Global Simulation Debugging Netlist Iterations Back-end Tools System Behavior Gantt Diagram Interaction Diagram Application Behavior Waveform

  16. APPLICATION APPLICATION [Lagadec, ESUG08] CDFG Use Tool X CDFG design CDFG EXPRESS model Tool Y HLL CDFG API (Java)‏ Platypus tool CDFG instances (STEP files)‏ ENTITY HierarchicalNode SUBTYPE OF (Node); localVariables : LIST OF AbstractData; subOperators : LIST [1 : ?] OF Node; END_ENTITY; ENTITY AccumulatorNode SUBTYPE OF (HierarchicalNode); init : AbstractData; --”AccumulatorNode.init” the initial value we start accumulating from. toBeAccumulated: AbstractData; DERIVE cumulatedArguments : LIST OF AbstractData := subOperators [ SIZEOF (subOperators)].outputs; WHERE toBeAccumulatedSource: SIZEOF ( cumulatedArguments )=1; typeCompat: cumulatedArguments[1].type = init.type; END_ENTITY; Target architecture description Madeo+ synthesis tool CDFG Checker HLL CDFG API (Smalltalk)‏ Target 1 EDIF Target 2 C like code Target 3 Specific Assembly code 16

  17. Application Intermediate Representation • Hierarchical Nodes • structuring  process  sequencing  loop  conditional • Atomic Nodes • compute  constants  memory access communications/synchronizations

  18. Application refinement at RTL Level • Low-level CDFG • Inherited from the CDFG framework • Produced from high-level CDFG mapping • Bound to an architecture • Additional constructs for hardware level • Primitive operators linked to libraries • Registers/flip-flop • FSM description (KISS format) • Random logic (BLIF format) • Taken as input of: • Synthesis tool  EDIF generation • RTL-level simulator

  19. Link between abstraction-levels • How keeping the link between HL-CDFG variables and LL-CDFG signals? ? Synthesis   Software abstraction Implementation in hardware

  20. Link between abstraction-levels • HL variable linked to its LL bit vector 1:n HL Variable Signal bit vector

  21. Multi-Level Simulation Engines • Behavioral specification of the application: Smalltalk • Direct execution by ST virtual machine environment • Use of system-level simulator API in code • High-level CDFG produced from Smalltalk code • Each node is simulated in function of sequencing nodes • CDFG API for design pattern: Visitor, Composite • Low-Level CDFG • RTL-Level simulator takes as input a low-level CDFG • Link between HL and LL CDFG • For example loop indices • Tracing signals • Waveforms generation

  22. System Modeling Framework • Component approach • Hierarchical composition • Modularity and reusability • Component characteristics • Declaration and scheduling of encapsulated processes • Port interfaces for connections and communications between components • Local communications between processes through local channels Component #Main Component #Unit2 Component #Unit1 P1 P1 P3 P2 P2

  23. System Modeling Framework Abstraction Level • Component class hierarchy • Connection class hierarchy Component Inheritance relation User Class #Main User Class #Unit1 User Class #Unit2 Abstraction Level Connection FIFO Blocking Channel

  24. System-Level Simulation • Framework of classes • Based on an event-driven simulation kernel [Blue Book] • Defines an API for simulating operator latencies, scheduling, stopping activities • System modeling framework inherits from the simulator • Simulator + modeling class hierarchy SimulationObject Simulation Component Connection User Model

  25. Example • Case Study • Partial modeling of a reconfigurable system-on-chip • System activities: DAM transfers, synchronizations, etc. • Application accelerated on a RA CPU DMA Memory Bus Local Mem. Reconfigurable Accelerator

  26. System simulation • Interaction diagram between components • Behavior of the system and the application

  27. LL-CDFG simulation • Cycle-accurate simulation • Stimuli on LL-CDFG signal interface defined in a method of the accelerator component • Interface between the system and accelerated function • Tracing values for LL-CDFG simulation • Simulator defines an API to set probes on the LL-CDFG signal interface • Tracing of the signal values • Graph generation

  28. Tracing signals • Traced signals and stimuli set through a GUI

  29. LL-CDFG simulation • Traces produced from signals • Values tested against expected results: SUnit testing

  30. Testing methodology: SUnit • Unit test for synthesis result • Characterization test between two simulations test1 selfshouldnt:[CDFGSynthesisAPIexample1] raise:TestResult error test2 CDFGSynthesisAPInew example:'example.step' family:'F4' primitives:true. res := selfreadResult. CDFGSynthesisAPInew example:'example.step' family:'F4' primitives: false. res2 := selfreadResult. self assert: res = res2

  31. Validation with manufacturer tools Smalltalk Method High-level CDFG Synthesis Low-level CDFG Export Mainstream/proprietary simulation tools (cell library) Netlist Back-end Tools

  32. Interfacing with third party tools • In a classical hardware design flow system activities interacting with the application’s interface are modeled in a wrapper • An hardware engineer would do: • Wrapper is hand-written in HDL (VHDL, Verilog) Time-consuming and error prone • Very low abstraction level and specific  Need deep update for new application • Increasing productivity by scripting and generating HDL wrapper • Interfacing with mainstream HDL simulation tools Wrapper Application Interface

  33. Stand-Alone LL Simulation • Dependencies on signals used for interacting with the LL-CDFG • Possibility to script execution scenarios through the instantiation of dependency objects triggering actions • No hardware details (signal declarations, etc.) • Set of interactions between the system and the application defined by a set of dependencies • Dependencies ~ mock object

  34. Wrapper Generation Smalltalk Method HL-CDFG Synthesis Multi-level simulator LL-CDFG Simulation script (Mock object creation) Export Netlist Verilog Wrapper Verilog ModelSim Results

  35. Dependency Model • Stopping the simulation • Triggering a signal on change Simulator onChange: (Simulator synthesizedCDFG outputNamed: 'done') relation: '=' value: 1 depName: 'Task Done’ action: Simulator stop. Simulator onChange: dma_Ack_Read relation: '=' value: 1 depName: 'dma_ack_read' action: (SimulatorForceSignal forceSignal: (dma_Req_Read) to: 0 in: 10).

  36. Generated HDL (Verilog) • Stopping the simulation • Triggering a signal on change • Looks shorter but is missing: signal declarations, module declarations, interconnections and other LL details  ST coding + generation enable to save 50% of the designer’s coding effort initial begin @(posedge done); - - HALT $stop end always @(posedge dma_ack_read) begin #(PERIOD * 10) dma_ack_read = 0; end

  37. Simulation by third party tools • Link: signal/LUT names LL-CDFG HL-CDFG  Enables to go back to the highest abstraction level Modelsim (Mentor Graphics)

  38. Outline • Overview of Reconfigurable Architectures • OO methodology for synthesis on RA • Simulation and testing methodology • Software-like debugging for RA • Conclusion

  39. After Testing Failed • Multi-level simulation enables to test the application at any flow stage • Use software engineering techniques • Testing at all level with SUnit • Modeling approach with generic models • Platform , application, interactions • Interfacing with third-party tools • Automated code generation • If validation failed… • …Time for debugging Testing Debugging

  40. Debugging and exploration facilities • Example: Visualworks’ debugger

  41. Methods and Tools for Software Debugging • Debugging facilities in Smalltalk environment • Conditional breakpoint and watchpoint inserted/modified dynamically • Hot-code replacement • Deep exploration of the execution context • Message stack control • Short iterative cycles: edit-compile-run-debug • Fast development • These software features do not exist in hardware • No symbolic debugging, no execution stack, etc.

  42. Debugging Hardware • Common hardware debugging methodology for RA • Hardware simulation, embedded logic analyzer… • Powerful tools but debugging is performed at hardware level  Trade-off performance/complexity exposed to the designer Complexity Hardware Software ELA ModelSim HDL Trade-off SystemC Performance

  43. From Software to Hardware Debugging • Reconfigurable circuits can support the main advantages of software engineering methodology • A bridge between software and hardware world • Reconfigurability enables to re-used the circuit • Possibility to iterate on a design • edit-compile-run ~ edit-synthesize/configure-run • Synthesis is time-consuming • Debugging the application in-situ with a specific interface  Gain in performance

  44. Global Flow Smalltalk Method High-level CDFG Probe Insertion Synthesis Low-level CDFG Multi-Level Simulator Export Probed Netlist Reconfigurable Architecture

  45. Probing Hardware : Principles • From software to hardware probes • Watchpoints and breakpoints concepts • Controllability over hardware execution • Software debugger features added to hardware application • Benefit from reconfigurability • Debugging support automatically inserted by the design framework (probes + controller) • All debugging features removed once design is validated

  46. Probing signals • Breakpoints set through a GUI

  47. Embedding software debugger features • Execution is controlled by the debugger • Breakpoints interfaced with a debug controller Op Op Op Op Schedule controller Synthesis   Simulator Op Op Debug ctrler Op Op Control interface Control interface

  48. Hardwired Breakpoint • Freeze the execution when triggered • Limit on conditional operators Hierarchical low-level CDFG Top Hier1 Hier2 i1 Op O i2 = != < > Value OpSel Conditionnal breakpoint i1 OpN O i2 = != < > Value OpSel Conditionnal breakpoint Global OR Control Enable operators Local Controller Debugging Controller

  49. Hardwired Breakpoint • Configurable breakpoints • Pool of probed signals is static • Breakpoint condition are configurable and can be enabled/disabled  Possibility to speculate and to backtrack execution • No-need for re-synthesis • Configuration structure • 2-D vector • Configuration word: contains operator selection, activation status and arguments • Extraction of the debug information: two execution modes • Running mode • Debug mode • Execution control: step-by-step, resume • Read back of the debugging information

  50. Hardwired Watchpoint • Probed signals are wired to the top interface • Automatically crosses the hierarchies • Possibly conditional • Trace analysis Hierarchical low-level CDFG Top Hier1 Hier2 Probed signal Op

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