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Reconfigurable Computing Platforms

Reconfigurable Computing Platforms. 施澤聰 R91922099 陳依蓉 D91922015. Outline. Reconfigurable computing platform FPGA General Purpose Processor General purpose processor reconfigurable computing techniques General purpose processor reconfigurable computing algorithms Future work reference.

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Reconfigurable Computing Platforms

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  1. Reconfigurable Computing Platforms 施澤聰 R91922099 陳依蓉 D91922015

  2. Outline • Reconfigurable computing platform • FPGA • General Purpose Processor • General purpose processor reconfigurable computing techniques • General purpose processor reconfigurable computing algorithms • Future work • reference

  3. FPGA reconfigurable computing platform • CoProcessor • CPU-CPU: can execute any algorithm(high flexibility) • CPU-ASIC: design for specific application(faster) • An alternative way • CPU-FPGA(Field-Programmable Gate Arrays) :software versatility and hardware performance

  4. FPGA applications • RSA • DES • FFT • DCT,IDCT • Neural network • And many others

  5. General Purpose Processor Platform • Based on prototyped or existing general purpose processor • Resource of GPP is not always used up • Program behavior is not identical • Not to hurt performance but save energy • Find the balance of performance and energy

  6. Reconfigurable Components on GPP • TLB • Cache • Instruction Queue • Functional Unit • Branch predictor • Pipeline

  7. Reconfigurable Instruction Queue • Joint local and global energy • Take advantage of some specific behavior of frame based applications • Try to adjust instruction queue according to current program behavior

  8. Reconfigurable Cache • Introduction to cache architecture • Techniques for reconfigurable cache • Algorithms to reconfigure cache

  9. Techniques for Reconfigurable Cache • Selective way • Turn off a way of cache • Selective set • Turn off sets of cache • Drowsy cache • A low power mode to keep data

  10. Algorithms to Use These Reconfigurable Cache Techniques • The execution of a program can usually be cut into different phases • Goal of these algorithms: • Try to find out or predict dynamically when and where to have phase change, and apply optimal configuration to that phase. • Advantage: Save Power

  11. (spec2K) gcc program behavior

  12. Two Direction to Find Phase Change • Temporal • To recursively profile program for a fixed interval • Spatial • Use the change of subroutines as phase change information

  13. Temporal Algorithms • Working set signature • Use executed PC to trace program behavior.

  14. Temporal Algorithm (cont.) • Phase tracking and prediction • Use the times of a basic blocks to be executed to trace program behavior.

  15. Spatial Algorithms • Positional adaptation of processors • Not to use fixed interval to profile • Try to identify important subroutines

  16. Future Work • Try to combine some application specific information to make phase change prediction more precise. • Combine both temporal and spatial method to improve phase change detection and prediction.

  17. References • Jean E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, P. Boucard, “Programmable Active Memories: Reconfigurable Systems Come of Age”, IEEE Trans. On VLSI, vol.4, pp.56~69, 1996. • J. Babb, R. Tessier, M. Dahl, S. Hanono, D. Hoki, A. Agarwal, “Logic Emulation with Virtual Wires”, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, vol.6, 1997. • D. Mange, E. Sanchez, A. Stauffer, G. Tempesti, P. Marchal, and C. Piquet, “Embryonics: A New Methodology for Designning Field-Programmable Gate Arrays with Self-Repair and Self-Replicating Properties”, IEEE Trans. On VLSI, vol. 6, 1998. • B. Xu and D. H. Albonesi, “Runtime Reconfiguration Techniques for Efficient General-Purpose Computation”, IEEE Design & Test of Computers, 2000. • S. H. Yang, M. D. Powell, B. Falsafi, and T. N. Vijaykumar, “Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay”, Proceedings of 8th International Symposium on High-Performance computer Architecture. • K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Cache: Simple Techniques for Reducing Leakage Power”, ISCA, 2002. • C. Zhang, F. Vahid, and W. Najjar, “A Highly-Configurable Cache Architecture for Embedded Systems”, ISCA, 2003.

  18. Reference • A. S. Dhodapkar and J. E. Smith, ”Managing Multi-Configuration Hardware via Dynamic Working Set Analysis”, Proceedings of 29th Annual International Symposium on Computer Architecture, 2002. • R. Sasanka, C. J. Hughes, and S. V. Adve, “Joint Local and Global Hardware Adaptations for Energy”, ASPLOS, 2002. • P. Ranganathan, S. Adve, and N. P. Jouppi, “Reconfigurable Caches and their Application to Media Processing”, ISCA 2000. • T. Sherwood, S. Sair, and B. Calder, “Phase Tracking and Prediction”, ISCA, 2003.

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