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Mikhail Talalay Konstantin Trushin Oleg Venger

Between Standard Cells and Transistors: Layout Templates for Regular Fabrics. Mikhail Talalay Konstantin Trushin Oleg Venger. SCL Russia Intel Corporation. Outline. Motivation Layout conventions and definitions Switch level transistor model Template based solutions Experimental results

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Mikhail Talalay Konstantin Trushin Oleg Venger

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  1. Between Standard Cells and Transistors: Layout Templates for Regular Fabrics Mikhail Talalay Konstantin Trushin Oleg Venger SCL Russia Intel Corporation

  2. Outline • Motivation • Layout conventions and definitions • Switch level transistor model • Template based solutions • Experimental results • Summary and future steps

  3. Motivation. Rayleigh criterion. CD - resolution limitation (critical dimension) λ – wavelength of the exposure tool NA – numerical aperture of the lens k – process related factor Constraints on layout during design: - unidirectional metals - equalized diffusion stripes - usage of repeatable blocks reduce value of “k” parameter and as the result“CD”.

  4. Layout conventions and definitions Regular layout layers N Common gates P Diffusion rectangles P N

  5. Layout conventions and definitions Regular layout layers N N Separated gates P P Diffusion rectangles P P N N

  6. Layout conventions and definitions Regular layout layers Repeatable blocks

  7. Layout conventions and definitions Template definition Template – is a routed regular block with selected input and output points Regular block inputs outputs ROUTING +input/output selection inputs outputs

  8. Layout conventions and definitions Example of logic function on template a b a b b a vcc vcc b vcc vss b c a a a

  9. Layout conventions and definitions Example of logic function on template c b a b c c b c a b a a b v c vcc ab b a ac vss a

  10. Switch level transistor model 5 states of a drain net vcc vss z lowvcc lowvss • z: high impedance (transistor is closed) • lowvcc=vcc–threshold voltage • lowvss=vss+threshold voltage vss vcc vcc vcc vss source source source source source vcc vss vcc vcc vss gate gate gate gate gate drain drain drain drain drain vss vcc z lowvcc lowvss

  11. Switch level transistor model source gate drain Truth table for P transistor source gate drain vss vss lowvss vss vcc z vss lowvss BAD vcc vss vcc lowvcc vss lowvcc … For each combination of states on source and on gate nets the state of drain net is identified. “BAD” – is special state, which means that this combination on source and gate is prohibited.

  12. Switch level transistor model State condition function For each vector of states on input pins the state of any net is identified, including output net. Each net of the schematic has its state defined if input pins values (state) are known. For each net we can define the conditions of each of 5 states as Boolean functions of input signals (plus function of BAD condition). We consider only circuits, where BAD = 0 for each net

  13. Switch level transistor model source gate drain State condition function, signal, operator

  14. Switch level transistor model State condition function, signal, operator left connection right

  15. Template based solutions Template functionality R(l,m,n) – number of logic functions with n essential variables, which can be implemented on template with size l, using input functions with no more than m input variables. R(2,1,2)=10 All 2 input functions were found. R(2,2,3)=218 All 3 input functions were found. R(2,1,3)=24 R(3,1,3)=72 108 different pairs of 2 input functions on templates with 2 outputs R(4,1,3)=160

  16. Concatenation of templates b b b b c c c c + + + + Connections, using identical input signals on diffusions: - using common power: Common power type c d a b c d a b vcc vcc vcc vcc vcc vcc vcc vcc + = cd ab cd ab vss vss vss vss Common power type - using common variable signal: Common input variables b a a b b a a b a b b a a b b a + = a b b a a b b a a a a a Common input variables

  17. Concatenation of templates b b c c + + Connections, using identical input signal and output signals on diffusions: Common inputs b a b b a b vcc vcc + vcc ab = vcc vcc vcc ab ab ab f f vss ab c vss c ab a a Common output and input

  18. Concatenation of templates Connections, using isolation gates: No common inputs Isolation gate b a a b b a vcc a b a b vcc vcc a b vcc vcc + = ab ab b a vss b a vss a b a b vss No common inputs Isolation gate

  19. Template based solutions Case study: full adder Template based solution:

  20. Experimental results Comparison between numbers of gates for CBD and template based solutions. Outputs number influence. More various properties of superposition operation for layout templates gives better ratio for circuits with several outputs.

  21. Future steps • Reveal physical parameters of a template: appropriate sizes of diffusions, number of routing tracks, metal rules • Research decomposition methodology of logic blocks on template structure • Prepare “fast” estimation engines for timing and power

  22. Thank YOU!

  23. Q&A

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