Robert Brayton Alan Mishchenko Niklas Een UC Berkeley

1. MagicAn Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Robert Brayton Alan Mishchenko Niklas Een UC Berkeley

2. Overview • Motivation • Big picture • Problem representation • Handling “Industrial stuff” • Clock domains, flop controls, boxes, etc • Algorithms • Sequential synthesis • Combinational synthesis with choices • Technology mapping • Minimum-perturbation retiming • Experimental results • Future work

3. Motivation • The baseline version of ABC is not applicable to industrial designs because it does not support • Complex flops • Multiple clock domains • Special objects (adders, RAMs, DSPs, etc) • Standard-cell libraries • A fresh start is needed, including • New design database should support these • New integration of application packages to reduce memory and runtime

4. Big Picture Verilog, EDIF, BLIF Programmable APIs A. Mishchenko, N. Een, R. K. Brayton, S. Jang, M. Ciesielski, and T. Daniel, "Magic: An industrial-strength logic optimization, technology mapping, and formal verification tool". Proc. IWLS'10.

5. Representations • Netlist • Original / current / resulting design • AIG: The main data-structure • Represents local / global functions • Gets synthesized / mapped/verified • Logic network • Represents the result of tech-mapping • AIG annotated with technology primitives (LUTs, gates, etc)

6. “Industrial Stuff” • Clock domains • Represent clock signal in the data-base • Annotate flops with their clock-domain number in the AIG • Separate clock domains in sequential transforms • Complex controls of the flops • Use parametrized flop model • Perform elaboration of control signals if needed • Handle asynchronous reset carefully! • Industrial primitives (adders, RAMs, DSPs, etc) • Use boxes (black/white, comb/seq, merge/no_merge, etc) • Currently propagates timing information, improves quality of synthesis • Elaborate boxes for seq synthesis, but do not map them • Need better support for user-specified attributes (don’t-touch, etc)

7. AIG: A Unifying Representation • An underlying data structure for various computations • Representing both local and global functions • Used in rewriting, resubstitution, simulation, SAT sweeping, induction, etc • A unifying representation for the whole flow • Synthesis, mapping, verification pass around AIGs • Stored multiple structures for mapping (‘AIG with choices’) • The main functional representation in ABC • Foundation of ‘contemporary’ logic synthesis • Source of ‘signature features’ (speed, scalability, etc)

8. d a b a c b c a c b d b c a d AIG Definition and Examples AIG is a Boolean network composed of two-input ANDs and inverters F(a,b,c,d) = ab + d(ac’+bc) 6 nodes 4 levels F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) 7 nodes 3 levels

9. c d c d a b a b Three Simple Tricks • Structural hashing • Makes sure AIG is stored in a compact form • Is applied during AIG construction • Propagates constants • Makes each node structurally unique • Complemented edges • Represents inverters as attributes on the edges • Leads to fast, uniform manipulation • Does not use memory for inverters • Increases logic sharing using DeMorgan’s rule • Memory allocation • Uses fixed amount of memory for each node • Can be done by a simple custom memory manager • Even dynamic fanout manipulation is supported! • Allocates memory for nodes in a topological order • Optimized for traversal in the same topological order • Small static memory footprint for many applications • Computes fanout information on demand Without hashing With hashing

10. Application Packages • Combinational optimization • AIG rewriting • Choice computation • Technology mapping • Sequential optimization • Retiming • Merging equivalence nodes • Technology mapping • Mapping with choices • Speedup • Verification • Simulation • Comb equivalence checking • Seq equivalence checking • Framework • Design database • File input / output • Programmable APIs

11. Sequential Synthesis • Detect, prove, and merge sequentially equivalent nodes • Comb equiv nodes are equivalent on for any state • Seq equiv nodes are equivalent only on reachable states • Observations • Can take into account user specified constraints (don’t-cares) • Leads to substantial reduction for large designs (> 10% in area) • Can be done using simulation and SAT (without BDDs) • Can be implemented efficiently for 1M gate designs A. Mishchenko, M. L. Case, R. K. Brayton, and S. Jang, "Scalable and scalably-verifiable sequential synthesis", Proc. ICCAD'08.

12. A A a c b a c a b Subgraph 2 Subgraph 1 Comb Synthesis With Choices • Restructure the AIG and keep track of changes • Iterate fast local AIG rewriting with a global view (via hash table) • Collect AIG snapshots and prove equivalences across them • Use equivalences (choices) during technology mapping • Observations • Leads to improved QoR after technology mapping • Successfully applied to 1M gate designs Pre-computing AIG subgraphs for F = abc Rewriting node A  a b a c a b c b c a Subgraph 2 Subgraph 1 Subgraph 3 A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06.

13. f LUT LUT  LUT e a c d b Primary outputs Choice node Primary inputs Technology Mapping Mapped network AIG f • Customizable structural mapping with priority cuts • Computes a small subset of cuts without impacting the QoR • Uses structural choices • Observations • Allows for controlling QoR tradeoffs, cost functions • Minimize delay/area, wire count, switching activity, etc • Successfully applied to 1M gate designs e c d b a A. Mishchenko, S. Cho, S. Chatterjee, R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07.

14. Delay Flops moved Minimum-Perturbation Retiming • Reduces delay after retiming, while minimizing the number of flops moved • Produces a trade-off: delay gain vs. the number of flops moved • Handles “industrial stuff” and retimes over white boxes! • Computes new initial state after backward retiming • Allows the user to control the resources • Desired delay gain • Maximum allowed number of flops moved • Maximum area increase after retiming • Observations • Can be useful before and after placement • Can be implemented efficiently • Runs in less than a minute for 1M gates S. Ray, A. Mishchenko, R. K. Brayton, S. Jang, and T. Daniel, "Minimum-perturbation retiming for delay optimization". Proc. IWLS'10.

15. Experimental Setup • Integrated Magic into an industrial FPGA synthesis flow • Experimented with the full flow, including P&R • Did not use retiming • Did not use post-placement re-synthesis • Verified by running Magic and in-house simulation tools • Experimented with 20 designs, from 175K to 648K LUT4 • Two experimental runs: • “Reference” stands for the typical industrial flow without Magic • “Magic” stands for the new flow with Magic Frontend Magic Backend Seq and comb synthesis, mapping, legalization Placement, routing, design rule checking, etc Design entry, high-level synthesis, quick mapping

16. Experimental Results

17. Cumulative Improvements • fMAX = 11.8% • LUT count = 12.7% • FF-to-FF level = 22.3% • Register count = 9.4% • Total flow runtime = 3.1% • P&R runtime = 50%

18. Future Work • Continue to improve application packages • AIG rewriting, tech-mapping, sequential synthesis, etc • Improve integration of logic and physical synthesis • Synthesis/mapping/retiming before placement • Retiming/restructuring after placement • Extend the flow to work for other technologies • Macro cells • Standard cells