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This research focuses on identifying symmetries in Boolean functions using circuit representation, simulation, and satisfiability. The proposed approach offers a comprehensive analysis leading to practical applications in logic synthesis and verification.
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Symmetry Detection for Large Boolean Functions Using Circuit Representation, Simulation and Satisfiability Jin S. Zhang, Portland State University Alan Mishchenko, UC Berkeley Robert Brayton, UC Berkeley Malgorzata Chrzanowska-Jeske, Portland State University Supported by: Maseeh Fellowship from PSU, NSF grant CCR-9988402 and CCR 0312676,SRC contract 1361.001, and by the California Micro program with our industrial sponsors, Altera, Intel, Magma, and Synplicity.
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Importance of Classical Symmetries • Widely used in logic synthesis and verification • BDD minimization • Decomposition • Boolean matching • Constructive logic synthesis • Placement & routing • Formal verification • …
Prior Work on Symmetry Computation • BDD-based methods [Möller ICCAD93, Panda ICCAD94, Tsai TCAD96, Mishchenko TCAD03] • BDD construction takes majority of run time • Cannot be applied to large designs • Incomplete circuit-based methods performing structural analysis [Wang, ICCD03] • Detect classical and higher-order symmetry • Complete circuit-based method using simulation and ATPG [Pomeranz, TCAD94] • Does not rely on recent improvements in SAT
Circuit Representation State-of-art SAT Solver Structural Analysis Bit-Parallel Simulation Transitivity Analysis Our Contributions Compute all classical two-variable symmetries for large Boolean functions
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Definitions • Completely specified Boolean function: • F (x1, …,xn) where x1, xn, F range over {0, 1}. • Supportof F: all the variables that F depends on. • Cofactors: • Cofactors w.r.t. variables xi and xj • F00 = F [xi 0, xj 0], • F01, F10, F11 are defined similarly.
x y y Representations of Boolean Functions • Binary Decision Diagram (BDD) • And-Inverter Graph (AIG)
F (…,x, y,…) = !F (…,y, x,…) • F01F10 = 1 Skew non-equivalent Skew equivalent Non-skew equivalent • F00F11 = 1 • F00F11 = 0 F (…,x, y,…) = !F (…,!y, !x,…) F (…,x, y,…) = F (…,!y, !x,…) Classical Symmetries For a pair of variables F (…,x, y,…) = F (…,y, x,…) • F01F10 = 0 Non-skew non-equivalent
F (…,x, y,…) = !F (…,y, x,…) • F01F10 = 1 Skew non-equivalent Skew equivalent Non-skew equivalent • F00F11 = 1 • F00F11 = 0 F (…,x, y,…) = !F (…,!y, !x,…) F (…,x, y,…) = F (…,!y, !x,…) Classical Symmetries For a pair of variables F (…,x, y,…) = F (…,y, x,…) • F01F10 = 0 Non-skew non-equivalent
S S S Transitivity of Symmetry Variables: a, b, c a b c Form larger symmetry group
Simulation • Computes the values of the internal signals and POs from the value of the PIs • Random / Guided • Control of simulation rounds • Static / Dynamic
Boolean Satisfiability (SAT) • Proves that a given Boolean formula has a satisfying assignment • F = (x+y)(y +z ), satisfying assignments: x = 1, y = 0 • SAT vs. BDDs • SAT involves search, heuristics can improve performance • BDDs “preprocess” the search space • By building canonical form of Boolean functions • Hard or impossible for large functions
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Compute functional support SAT returns counter-example? Perform guided simulation Y Perform structural analysis N Perform random simulation N All variable pairs processed? All variable pairs processed? Y N returnall symmetric pairs Y returnall symmetric pairs Overview of the Algorithm Derivenetwork AIG Call SAT for a remaining pair
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Structural Analysis: Detect Symmetric Variable Pairs • Convert AIGs to Implication Supergates (ISs) • Introduced in [Chang DAC00] • Compute local symmetries for each Implication Supergates • Propagate global symmetries from primary inputs to primary outputs
AIG e a d b c Represents 2-input AND gate AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached
AIG e a d b c Represents 2-input AND gate AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached
AIG e a d b c Represents 2-input AND gate AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached AIG e a d b c Represents 2-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached Implication supergate AIG s1 e a b c e s2 a d b c Represents 2-input AND gate Represents multi-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached Implication supergate AIG s1 e a b c e s2 d a d b c Represents 2-input AND gate Represents multi-input AND gate
AIG Implication Supergates • Expand the AND gate until a PI or complemented edge is reached • Recover lost structural symmetry in AIG Implication supergate AIG s1 e a b c e s2 s3 d a d b c b c Represents 2-input AND gate Represents multi-input AND gate
IS Positive PIs Negated PIs Other ISs Candidate Symmetry Kept Symmetry Final Symmetry s3 b,c (b,c) (b,c) s2 d s3 (b,c) s1 b,c,e a s2 (b,c) (b,e) (c,e) (b,c) (b,c) Structural Symmetry Detection IS • Divide the fanins of each IS into three categories: • - Positive PIs • - Negated PIs • - Other ISs s1 e a b c s2 d s3 b c
IS Positive PIs Negated PIs Other ISs Candidate Symmetry Kept Symmetry Final Symmetry s3 b,c (b,c) (b,c) s2 d s3 (b,c) s1 b,c,e a s2 (b,c) (b,e) (c,e) (b,c) (b,c) Structural Symmetry Detection IS 2. Identify initial candidate symmetric pairs for each IS: - Pair up variables in positive and negative PIs separately s1 e a b c s2 d s3 b c
IS Positive PIs Negated PIs Other ISs Candidate Symmetry Kept Symmetry Final Symmetry s3 b,c (b,c) (b,c) s2 d s3 (b,c) s1 b,c,e a s2 (b,c) (b,e) (c,e) (b,c) (b,c) Structural Symmetry Detection IS 3. Keep a symmetric pair if the variables: - not in the support of other IS or - symmetric for each fanin in other IS s1 e a b c s2 d s3 b c
IS Positive PIs Negated PIs Other ISs Candidate Symmetry Kept Symmetry Final Symmetry s3 b,c (b,c) (b,c) s2 d s3 (b,c) s1 b,c,e a s2 (b,c) (b,e) (c,e) (b,c) (b,c) Structural Symmetry Detection IS 4. Propagate the symmetric pairs to its parent IS if: - the symmetry holds for at least one fanin of the other IS, and - the variables are not in the support for other fanins s1 e a b c s2 d s3 b c
Summary: Structural Analysis • Detect symmetry in one sweep over the circuit • Discover most easy structural symmetries • Simpler, faster and more scalable than [Wang ICCD03] • We only compute classical symmetries
Outline • Motivations • Background • Our approach to symmetry computation • Structural analysis • Simulation • Transitivity analysis • SAT • Experimental results • Conclusions
Simulation: Detect Non-symmetric Variable Pairs • Random & guided simulation • Performance random simulation until saturation • Guided simulation uses SAT counter examples and their distance-1 patterns • E.g. Distance-1 patterns of “011” are “111”, “001”, “010”
Why Distance-1 Patterns? • For a realistic and sparse function • Realistic: appear in practical circuit • Sparse: many 0s and fewer 1s or vice versa
Why Distance-1 Patterns? • For a realistic and sparse function • Random simulation often fails
Why Distance-1 Patterns? • For a realistic and sparse function • Random simulation often fails • SAT counterexamples reach unlikely values
Why Distance-1 Patterns? • For a realistic and sparse function • Random simulation often fails • SAT counterexamples reach unlikely values • Distance-1 patterns represent its neighborhood, contain other unlikely values
0101 1101 Simulation:Detect Non-symmetric Variable Pairs • Random & guided simulation • Bit-Parallel computation • Simulating one AIG node involves bit-wise operations • Simulate 32 or 64 bits simultaneously 1010
Simulation:Detect Non-symmetric Variable Pairs • Random & guided simulation • Bit-Parallel computation • One vector targets all variable pairs simultaneously
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 ab cd 00 01 11 10 00 0 0 1 0 01 0 0 1 1 (4) Simulate the above patterns 0 11 1 1 0 0 10 0 1 0 • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab cd 00 01 11 10 00 0 0 1 0 01 0 0 1 1 (4) Simulate the above patterns 0 11 1 1 0 0 10 0 1 0 • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab 1 cd 00 01 11 10 00 0 0 1 0 01 0 0 1 1 (4) Simulate the above patterns 0 11 1 1 0 0 10 0 1 0 • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab 1 cd 00 01 11 10 1 00 0 0 1 0 01 0 0 1 1 (4) Simulate the above patterns 0 11 1 1 0 0 10 0 1 0 • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab 1 cd 00 01 11 10 1 00 0 0 1 0 0 01 0 0 1 1 (4) Simulate the above patterns R = 0110 0 11 1 1 0 0 10 0 1 0 • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab 1 cd 00 01 11 10 1 00 0 0 1 0 0 01 0 0 1 1 (4) Simulate the above patterns R = 0110 0 11 1 1 0 0 10 0 1 0 (5) Check variable pairs with the same polarity in P: {a, c}, {a, d}, {c, d} • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
Simulation Example F(a, b, c, d) = ab + d (ac+ bc) (3) Flip the bits on the diagonal: 0011 1111 1001 1010 0 ab 1 cd 00 01 11 10 1 00 0 0 1 0 0 01 0 0 1 1 (4) Simulate the above patterns R = 0110 0 11 1 1 0 0 10 0 1 0 (5) Check variable pairs with the same polarity in P: {a, c}, {a, d}, {c, d} • Suppose the vector P is 1011. (2) Create the bit matrix: a b c d 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 (6) non-symmetric pairs: {a, c}, {c, d}