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CHAPTER 10

CHAPTER 10. Computer Organization. Introduction . Computer Architecture – How computers should be configured and what features should be included. Included are the – Lengths of the instruction words how many addresses in memory are referenced by an instruction word.

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CHAPTER 10

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  1. CHAPTER 10 Computer Organization

  2. Introduction • Computer Architecture – How computers should be configured and what features should be included. • Included are the – • Lengths of the instruction words • how many addresses in memory are referenced by an instruction word. • Number of bits in each memory word • Size of Instructions & data words • Form of numbers • Instructions provided • Memory organization • Interface of Input – Output devices

  3. Instruction Word Format-Number Of Addresses • Two address instructions • Many computers have two – address instruction words with three sections.(Fig 10.1) • The three sections are – • OP code • Address 1 • Address 2

  4. Two Address Instructions • Different computers use these addresses differently. • Instead of single accumulator, there can be two or more registers called multiple accumulators or general – purpose registers. • Results are generally stored in the general register (accumulator) • In some computers, instruction words are provided in which each of the two addresses refer to general registers.

  5. Zero Address Instructions - Stack • Zero Address Instructions • The instruction word does not specify any location in memory for an operand • It relies in stack to provide operands • Stack is a set of consecutive locations in a memory into which operands can be placed • The first operand placed on the stack is said to be at the bottom of the stack

  6. Zero Address Instructions - Stack • Placing an operand on the stack is called pushing. • Removing an operand is called popping the operand. • Most recently placed operand is said to be on the top of the stack. • Stack works on LIFO principle.

  7. Zero Address Instructions - Stack • Fig 10.2 shows the operation of a stack • Each word in the stack has a fixed length and a address

  8. Zero Address Instructions - Stack • Stack Pointer – It is a register which contains the address of the top operand in the stack • The stack pointer is incremented or decremented when an operand is pushed or popped • eg To execute ADD instruction, the top two operands in the stack will be removed, added and then the sum is placed on the top of the stack • Stacked computers include the Burroughs 5500,1700 and the Hewlett Packard 3000. • Stacks are widely used in other sections of computers also

  9. Instructions & Data • 6100 has a 12 bit / word memory,12 bit instruction words with a 3 bit OP code. • CDC produces a number of 64 bit / word large computers with same basic structures as well as some smaller 24 bit / word computers • CRAY also makes computers of this types

  10. Instructions & Data • To conserve on instruction word length and also permit storing of strings of characters of arbitrary length, most small computers now have memory words of 8 bits per word • Instruction words are of variable length with each being some multiple of 8 bits • Data words are also multiple of 8 bits with many microprocessors having 8, 16 & 32 bit words

  11. Addressing Techniques • Several techniques are used • These techniques are generally motivated by one of the following considerations • Desire to shorten address sub-section • Programmer convenience • System operating facilities • To efficiently load and remove these programs from memory in different locations, addressing techniques are provided which make them re-locatable

  12. Direct Addressing • Simply giving the complete binary address in the memory is the most direct way to locate an operand or to give an address to jump to. • Most computers have some form of direct addressing • Address field contains address of operand • Effective address (EA) = address field (A) e.g. ADD A • Add contents of cell A to accumulator • Look in memory at address A for operand • Single memory reference to access data • No additional calculations to work out effective address • Limited address space

  13. Direct Addressing Diagram Instruction Opcode Address A Memory Operand

  14. Direct Addressing • Example 1 ( 8080 microprocessor ) • It has a single 8 bit accumulator. • It’s memory is organized into words of 8 bits each (called bytes). • OP code in this occupies 8 bits (1 byte)/ entire memory location. • The address bits are then located in the following memory locations. • Since 216 Words can be used in a memory so 2 bytes are required for a direct address . • Therefore, a direct address instruction requires 3 bytes in memory – one for OP code and two for the direct address.

  15. Direct Addressing • Example 1 ( 8080 microprocessor ) contd. • While executing the instruction , 8080 CPU always obtains the OP code from memory first. • Now CPU reads the necessary bytes from memory ,assembles each instruction word in its registers, and then execute. • A typical direct access instruction in the 8080 is the LDA (load accumulator ) instruction with OP code 00111010 (3A hexadecimal). • This OP code is followed by 2 bytes giving the address in memory to be loaded into the accumulator. • The low order(least significant ) bits of the address are given in the first byte of the address and high order in the second byte.

  16. Direct Addressing • Example 1 ( 8080 microprocessor ) contd. • Assume that the memory contains these values – • The three bytes in locations 245, 246, 247 contain a single LDA instruction which , when executed , will cause the value 2316 to be transferred into the accumulator of the 8080 microprocessor. .

  17. Direct Addressing • Example 2 ( 6800 microprocessor ) • It has two 8-bit accumulators known as accumulator A and accumulator B. • It has 8 bits per memory word. • The OP code of the instruction occupies 8 bits (a complete memory word). • The address bits for an instruction word follow the OP code in the memory location. • The memory can be 216in size.

  18. Direct Addressing • Example 2 ( 6800 microprocessor ) contd. • eg,. OP code for ADDA (which causes the contents of the address referenced to be added to and then stored in the accumulator A) is BB(hexadecimal) , or 10111011 (binary). (refer fig 10.3) • If the CPU reads an OP code of BB , it then reads the next 2 bytes in memory to obtain the address. • It then performs the required addition.

  19. Direct Addressing

  20. Direct Addressing • Example 2 ( 6800 microprocessor ) contd. • Some instructions have only implied addresses(HALT ) is such an instruction. • The microprocessor first reads the OP code to determine how many more locations from the memory need to be read from the instruction word This microprocessor also has instructions with only 8 bit addresses. • Motorola , in its manual, calls 8 bit address instruction words direct-addressing instructions and the 16 bit address instruction words extended direct- addressing instructions. • 16 bit addressing technique is more natural and the memory can be reached.

  21. PDP-11 processor • All operand addressing is accomplished through the general purpose registers. • One of the eight registers is selected to specify the location of the data.(An operand address). • Each instruction specifies the : • Function to be performed • General purpose register to be used when locating the source operand and / or destination operand. • Addressing mode , which specifies how the selected registers are to be used.

  22. Direct Addressing • Example 3 (PDP-11) DEC product • PDP-11/05 is a small computer, PDP-11/45 is a medium sized and PDP-11/70 is a large system. • It has eight 16-Bit general registers (accumulators) named as R0 – R7. • Its memory is organized into 8 bit words (1 byte in each memory location) • A typical direct address instruction in the PDP-11 involves adding the numbers in two general registers and storing the sum in one of the registers

  23. Direct Addressing • Example 3 (PDP-11) DEC product • The instruction word has three sections : OP code,source address and destination address. • E.g. In an ADD , the number in the source register is added to that in the destination register , and the sum is placed in the destination register. • Source and destination are general registers,and there are total eight general registers, so three extra bits are included in each of the source and destination addresses to tell which addressing mode is to be used. • The instruction format is as follows –

  24. Direct Addressing • Example 3 (PDP-11) DEC product • The first leftmost 3 bits in the source and destination addresses give the mode, and for direct addressing they will be 000. • The next 3 bits are register number . • The OP code for ADD in PDP-11 is 0110 and so the instruction word which will add register 3 to register 5 and store the sum in register 5 is

  25. Direct Addressing • Example 3 (PDP-11) DEC product • Another example of direct addressing is the increment instruction, which simply adds 1 to a selected general register. • The instruction word in this case has two sections: an OP code and an address section. • The address section has three bits to tell the mode and three bits to designate the register. • The OP code for an INC(increment ) instruction is 0000101010. • Thus an instruction that will increment general register 5 is

  26. Immediate Addressing • A simple way to obtain an operand is simply to have it follow the instruction word in memory. • E.g. If we want to add the no 7 to the accumulator in a single accumulator computer, and the memory is organized in 8 bits location each. • Simplest way would be to have an 8-bit OP code which says to ADD and then the augend follows immediately in memory (in the next byte). • The computer would then read the OP code , get the augend 7,add it into the accumulator, and take the next instruction byte from the location following the location of the previous augend 7. • This is the way 8080 and 6800 computers operate.

  27. Immediate Addressing • Operand is part of instruction • Operand = address field • e.g. ADD 5 • Add 5 to contents of accumulator • 5 is operand • No memory reference to fetch data • Fast • Limited range Instruction Opcode Operand

  28. Immediate Addressing • Example 1 (8080 microprocessor) • The instruction ADI(add immediate ) has OP code 11000110 . • It tells the CPU to take the byte following this OP code and add it into the accumulator • E.g. • At address 1616 in memory , it reads the OP code, and sees it is ADI instruction, takes the next byte from the memory which is 00001100, adds it into accumulator , and takes the next OP code from location 1816 in memory.

  29. Immediate Addressing • Example 2 (6800 microprocessor) • It has two accumulators , and OP code tells which accumulator to use. • E.g. The instruction ANDA with OP code 8416 will cause the byte following the OP code to be ANDed bit by bit with accumulator A. • The instruction ANDB with OP code C416 will cause the byte following the OP code to be ANDed bit by bit with accumulator B.

  30. Immediate Addressing • Example 2 (6800 microprocessor)contd. • E.g. Sup. That accumulator A contains 01100111 and accumulator B 10011101. • Then consider the memory • It will read the ANDA at location 1016 and AND the next byte with accumulator A, giving 01000101,which will be placed in accumulator A. • It will now read the ANDB in location 1216, AND the next byte with B to give 10000101, place this in accumulator B,and read the next OP code for an instruction from location 1416.

  31. Immediate Addressing • Example 3(PDP-11 microprocessor) • It has 8 accumulators so must tell which accumulator to use while executing the instruction. • First three bits in the source and destination address sections will tell the addressing mode. • The OP code of ADD instruction is the same for direct and immediate addressing in PDP-11. • E.g. The OP code for ADD is 0110 and an instruction word for an immediate add looks like this :

  32. Immediate Addressing • Example 3(PDP-11 microprocessor) contd. • The source bit shows that the add is an immediate add and the augend is in the following word. • Destination section here refers to general register 3, so the next 16 bits will be added into general register 3. • E.g If we place 101 in the rightmost bits instead of 011, it will cause an addition into general register 5.

  33. PDP-11 processor(Immediate addressing) • Register 7 is both a general purpose register and the program counter on the PDP-11. • When CPU uses the PC to access a word from memory, the PC is automatically incremented by 2 to contain the address of the next word of the instruction to be executed. • Some value is located at the second word of the instruction and is added to the contents of the register mentioned in the register. • The processor fetches the first word and increments the PC by 2. • The source operand mode is 27(autoincrement the PC).

  34. PDP-11 processor(Immediate addressing) • Example1 • Consider that general register 4 contains 0000618, and memory is as above.(No’s are in octal). • Execution of these by CPU will result in 128 being added into general register 4, giving 738 in that register.

  35. Relative Addressing • The address part of the instruction word gives a number to be added to the address following the instruction word. • Thus, the address section contains a displacement from the instruction words location in the memory. • Giving only a displacement reduces the number of address bits but makes only a part of the memory available. • For better understanding refer to examples.

  36. Relative Addressing • Example 1( 6800 microprocessor) • It can have up to 216 memory words, so 16 bits are required to address the entire memory in a direct mode. • In this addressing the address is reduced to an 8-bit displacement, shortening the instruction word. • In 6800 a relative – address instruction word contains only the OP code and an 8-bit address, so only two locations in memory are required. • The OP code tells what type of addressing is used. • The address in the second byte of the instruction is added to the address at which the OP code lies plus 2.

  37. Relative Addressing • Example 1(6800 microprocessor) contd. • The OP code for a Branch instruction with relative addressing is 20(hexadecimal). • The microprocessor would read the OP code at location 10. • Get 00000101 from the next memory location, add this 5(decimal) to 2 plus 10 (where the OP code lies), giving 17. • Next OP code will then come from location 17. E.g. (refer fig.10.6)

  38. Relative Addressing • Example2(PDP-11microprocessor) • A relative addressing mode can be used for the INC(increment) instruction . • The OP code for INC in the PDP-11 is 0052 in octal and 278 in address part indicates a relative addressing mode. • E.g Assume the following situation in memory • The displacement ,128 here , is added to the address following the instruction word, here it will be 1024. • This gives 1036, and so the number at location 1036 in memory would be incremented. 005227

  39. Indirect Addressing • It causes the instruction word to give the address , but of the address of the operand. • E.g. If we write IAD 302(indirect add) then the number stored at address 302 will give the address of the operand to be used. • E.g When the instruction word at address 5 in the memory in the following program is performed, it will cause the number 164 to be added to the current contents of the accumulator.

  40. Indirect Addressing • Example 1 (6100 microprocessor) • It has a 12 bit instruction word,therefore the entire 4096 word memory is accessible to the instruction word.(Fig. 10.7). • The instruction word contains a 3-bit OP code , a page bit, an indirect bit, and a 7-bit unsigned binary number. • A zero in indirect bit says that there is no indirect addressing. • E.g. The TAD instruction with OP code 001 ,a page bit is 0, (so the address is on page 0 in the memory) is shown.

  41. Indirect Addressing • Example 1 (6100 microprocessor) contd. • The 7 address bits point to location 628 , and that location contains the address of the operand. • At location 628 we find 34328, and it is the location ,at which the operand 3255, is located, that is added to the accumulator.

  42. Indirect Addressing • Example 2 (8080 microprocessor) • In this processor , there are several registers in the CPU in addition to the accumulator called scratchpad registers. • These registers are named B,C,D,E,H,L, of 8 bits each in length. • Sometimes they can be handled in pairs with a resultant length of 16 bits (forming a complete address). • E.g. A MOV(move) instruction , which moves an 8-bit word from the memory into a designated register . The format for this instruction word is as follows: • OP designation source • 01 DDD 110 • The DD section here is 3-bits,accumulator

  43. Indirect Addressing • Example 2 (8080 microprocessor) contd. • The DD section here is 3-bits,accumulator . • The accumulator has no 111, register B has number 000, scratchpad register C has number 001, etc. • The location in the memory from which the word to be moved is taken is always given by the register pair H,L. Thus if register pair H,L contains 45A216 (H contains 45,L contains A2), then the address in memory used will be 45A216. • E.g If the instruction word is 01111110 and register pair H,L contains 374216 ,then the word at location 374216 will be moved into the accumulator. • If the instruction word is 01001110,and the H, L pair contains 237916, then the word at location 237916 in memory will be moved into scratchpad register C.

  44. Direct and Indirect addressing example • Addressing Mode

  45. Indexed Addressing • Indexing was first used in a computer developed at the university of Manchester. • A register named the B box was added to the control section. • The U.S.term for B-box is index register. • The address of the operand located in memory would be at the address written by the programmer plus the contents of the B-box. • Computers sometimes provide several index registers.

  46. Indexed Addressing • Use of index registers eases writing programs that process data in tables , greatly reducing the number of instructions required in an iterative program. • When index registers are included in a computer, a section of the instruction word tells the computer whether an index register is to be used and if so, which one. • The basic instruction word is broken , for a single – address computer, into three parts instead of two. (Fig. 10.8)

  47. Indexed Addressing • If an index register is not to be used, 0s are placed in the index register designation section of the word. • Two instructions are introduced , to describe the operation of the index registers. • One of these instructions is designated by the mnemonic code SIR(set index registers). This will cause the address section of the instruction word to be transferred into the index register designated by the index register designation bits in the word. • E.g. 01 SIR 300 will load the number 300 into index register 01. • Second instruction is designated with the mnemonic code BRI (branch on index).This will cause the contents of the index register designated to be decreased by 1 if the number stored in the index register is positive.At the same time , the computer will branch to the address in the address section of the instruction word, taking its next instruction from that address. • If the index register designated contains a 0, the computer will not branch but will perform the next instruction in normal order.

  48. Indexed Addressing • E.g. If index register 01 contains 300 and we write a CAD(clear and add) instruction 01 CAD 200 • Then the computer will add the contents of index register 01 to the contents of the address section, and the address used will be the total of these two. • Since register 01 contains 300 and the address section contains 200, the address from which the operand will be taken will be address 500 in memory. • For example refer to table 10.1,which will add the numbers stored in memory addresses 201 to 300 and store the sum in address 301.

  49. Indexed Addressing

  50. Indexed Addressing • Example1 (6800 microprocessor) • It has a single16 –bit index register. • When indexing is used for ADDA instruction , the OP code is AB(hexadecimal) . • This instruction has only one 8-bit address part, so entire instruction word requires only 16 bits (two memory locations).

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