CHAPTER 2

1. CHAPTER 2 Introduction to Counter By : Pn Siti Nor Diana Ismail

2. Introduction • A counter– a group of flip-flops connected together to perform counting operations. • The number of flip-flops used and the way in which they are connected determine the number of states (modulus). • Two broad categories according to the way they are clocked • They classified into two categories i. Asynchronous counter – do not have fix time with each other ii. Synchronous counter – have a fix time with each other

3. Differences between Asynchronous and Synchronous counter

4. (i) Asynchronous Counter • Commonly called ripple counter • First FF is clocked by external clock pulse • Then each successive FF is clocked by output of preceding FF.

5. Example 1 : 2-bit Asynchronous Binary Counter

6. Timing Diagram • Main clock pulse only applied to FF0. • Clock for next FF, taken from previous complemented output Q. • All inputs (J, K) are high (Vcc). • 2nd FF is triggered by Q0’ output of FF0. • FF0 change state at positive-going edge each clock pulse but FF1 only change state when triggered by positive-going transition of Q0’ output FF0. • Transition of clock pulse and transition of Q0’ FF0 can never occurs at same time.

7. Timing Diagram (cont’d)

8. Timing Diagram (cont’d) • Positive-edge CLK1 cause Q0 output FF0 HIGH at same time Q0’ goes LOW but no effect FF1 bcoz positive edge transtion must occur to trigger FF. • After leading edge CLK1, Q0= LOW, Q0’= HIGH bcoz in toggle condition. • At CLK2 cause Q0= LOW, Q0’= HIGH. It can triggered FF1 and Q1= HIGH. • After leading edge CLK2, Q0=0, Q0’=1 and Q1=1 • Positive-edge CLK3 cause Q0=HIGH bcoz JK FF in toggle mode, So the output Q0’=LOW, So FF1 no effected. • At CLK4, Q0=LOW, So Q0’=HIGH and trigger FF1, Q1=0 • After leading edge CLK4, Q0=0 and Q1=0. • Counter now recycled to origin state and both FF are RESET.

9. Binary State Sequence Term recycled = applied to counter operation and it refer to transition of counter from it final state back to original state.

10. Example 2: 3-bit Asynchronous Binary Counter and timing diagram for one cycle

11. State sequence for a 3-bit binary counter

12. Propagation delays in 3-bit binary counter

13. Asynchronous Decade Counter • The modulusof a counter is the number of unique states that the counter will sequence through. • The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops. • Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence. • Counter with ten states are called decade counter. • To obtain a truncated sequence it is necessary to force the counter to recyclebefore going through all of its possible states.

14. Example 1 : 4-bit Asynchronous decade counter

15. (ii). Synchronous Counter Synchronous counter • - clock input connected to all FF. • - so, they are clock simultaneously.

16. Example 1 : 2-bit Synchronous counter Toggle (0 to 1)Toggle (1 to 0)Toggle (0 to 1)Toggle (0 to 1) Toggle (0 to 1)Toggle (1 to 0)

17. Binary state sequence

18. Example 2: 3-bit synchronous counter 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0

19. Binary state sequence for 3-bit binary counter

20. Example 3: A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

21. Example 4: 4-bit synchronous BCD Decade counter

22. Operation : • FF0 ; - Q0 toggle with each clock pulse because J0=K0=1 • FF1; - Q1 changes only when Q0=1,Q3=0. - That’s why J1=K1=Q0Q3’ • FF2; - Q2 changes only when both Q0=1,Q1=1 - That’s why J2=K2=Q0Q1 • FF3; - Q3 changes only when both; Q0=1,Q1=1,Q2=1 or Q0=1,Q3=1

23. State sequence for 4-bit synchronous BCD Decade counter

24. Assignment 1