APLACE: A General and Extensible Large-Scale Placer

1. APLACE: A General and Extensible Large-Scale Placer Andrew B. Kahng Sherief Reda Qinke Wang VLSICAD lab University of CA, San Diego

2. Goals and Plan Goals: • Scalable and robust implementation • Leave no stone unturned / QOR on the table • Leave nothing for competitors Plan and Schedule: • Use APlace as an initial framework • One month for coding + one month for tuning

3. Implementation Framework New APlace Flow • APlace weaknesses: • Weak clustering • Poor legalization / detailed placement Clustering Adaptive APlace engine Global Phase Unclustering • New APlace: • New clustering • Adaptive parameter setting for scalability • New legalization + iterative detailed placement Legalization WS arrangement Detailed Phase Cell order polishing Global moving

4. Clustering/Unclustering • A multi-level paradigm with clustering ratio = 10 • Top-level clusters  2000 • Similar in spirit to [HuM04] and [AlpertKNRV05] Algorithm Sketch • For each clustering level: • Calculate the clustering score of each node to its • neighbors based on the number of connections • Sort all scores and process nodes in order as long as cluster size upper bounds are not violated • If a node’s score needs updating then update score and insert in order

5. Adaptive Tuning / Legalization Adaptive Parameterization: • Automatically decide the initial weight for the wirelength objective according to the gradients • Decrease wirelength weight based on the current placement process Legalization: • Sort all cells from left to right: move each cell in order (or a group of cells) to the closest legal position(s) • Sort all cells from right to left: move each cell in order (or a group of cells) to the closest legal position(s) • Pick the best of (1) and (2)

6. Detailed Placement Whitespace Compaction: • For each layout row: • Optimally arrange whitespace to minimize wirelength while maintaining relative cell order. [KahngTZ99], [KahngRM04]. Cell Order Polishing: • For a window of neighboring cells • Optimally arrange cell orders and whitespace to minimize wirelength Global Moving: • Optimally move a cell to a better available position to minimize wirelength

7. Parameterization and Parallelizing Tuning Knobs: • Clustering ratio, # top-level clusters, cluster area constraints • Initial wirelength weight, wirelength weight reduction ratio • Max # CG iterations for each wirelength weight • Target placement discrepancy • Detailed placement parameters, etc. Resources: • SDSC ROCKS Cluster: 8 Xeon CPUs at 2.8GHz • Michigan Prof. Sylvester’s Group: 8 various CPUs • UCSD FWGrid: 60 Opteron CPUs at 1.6GHz • UCSD VLSICAD Group: 8 Xeon CPUs at 2.4GHz Wirelength Improvement after Tuning : 2-3%

8. Artificial Benchmark Synthesis • Created a number of artificial benchmarks to test code scalability and performance • Used statistics of benchmarks to create synthesized versions of bigblue3 and bigblue4 • Mimicked fixed blocks layout diagrams in the artificial benchmark synthesis • Proved useful since we identified a problem in clustering if there are many fixed blocks

9. Results

10. Bigblue4 Placement HPWL = 833.21