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Fiber Road Card & L3 Buffering

Fiber Road Card & L3 Buffering. H.Evans Columbia U. FRC Tasks Communicate with SCL Receive L1CTT Information Distribute Trigger/Road Info to System Control All Data Transfers to L3 Special VME Arbitration: VBD – CPU Implementation PMC Daughterboard on Motherboard Modest FPGAs + FIFOs

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Fiber Road Card & L3 Buffering

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  1. Fiber Road Card& L3 Buffering H.Evans Columbia U. FRC Tasks • Communicate with SCL • Receive L1CTT Information • Distribute Trigger/Road Info to System • Control All Data Transfers to L3 • Special VME Arbitration: VBD – CPU Implementation • PMC Daughterboard on Motherboard • Modest FPGAs + FIFOs The Columbia/Nevis Team • Physicists: • Hal Evans (faculty) • Georg Steinbrück (postdoc) • Maurice Leutenegger (student) • Engineers: Qi An, Bill Sippach • Full Nevis Support STT Review: 25-Feb-00

  2. FRC Functional View SCL HUB L1CTT SCL Mezzanine Card VTM (PMC J6) PCI Reg's PCI Reg's VTM Ctrl/Stat G-L Data 16+4 Data/Status 128 Road Receiver SCL Format & Control Status L1CTT Data 16+2 SCL Init L1/L2 Data 44 Ctrl Error L1 Data SCL Smart Fanout 40 Ctrl T/R Data Formatter L1/L2 Data 44 Ctrl PCI Reg's T/R Data Ctrl 32+2 T/R Data Fanout Buffer Manager VME Serial VBD Start PCI Reg's 32+2 Ctrl T/R Data Message Status 10 12+1 J3 Aux Bus (PMC J4B) PCI Bus 3 Interface PCI Bus 1,2 Interface Bus Arbitration VBD Start Local BC's LVDS Tx's VBD Busy VBD Busy Universe II VME-PCI FRC L3 Buffer CPU VBD STT Review: 25-Feb-00

  3. On the Motherboard L1CTT Roads IN BM Signals Local BC SCL IN Trig/Road OUT STT Review: 25-Feb-00

  4. Communications Paths STT Review: 25-Feb-00

  5. Timing STT Review: 25-Feb-00

  6. T/R Data – Block Functions • Event Synch  All Boards • Roads  STCs (assoc. hits)  TFCs (sent to L2CTT) L1CTT Road FIFO All Road Data 16+2 M U X Filter 16+2 32+2 EF/FF/AF Ctrl BOE EOE BX TURN Header Trailer BX EVT_MTCH Compare Control 16+2 EF/FF/AF L1_BX L1_TURN Error CSR DR/MR L1_QUAL 40+2 Filter PCI 3 Bus PCI 1,2 Bus SCL FIFO BOE EOE VME LVDS Tx's SCLF STT Review: 25-Feb-00

  7. T/R Data – Flow Wait CTT FIFO Wait SCL FIFO EF=0 EF=0 not (BOE&EOE) • Read CTT Data • verify BOE & EOE • Read SCL Data • verify BOE & EOE L1_QUAL • CTT Error • set Trailer bit • advise SCL ? L1_BX/TURN • SCL Error • set Trailer bit • advise SCL ? BX/TURN Compare Evt No's Wait Token & Data Construct Header not Equal • Evt Error • set Trailer bit • advise SCL ? Construct Trailer Wait Token & Data Wait Token & Data • Data to oFIFO • Token to Trailer • Trailer to oFIFO • Token to Header • Header to oFIFO • Token to CTT STT Review: 25-Feb-00

  8. T/R Data Format • Trigger Info • L1 Qual Processing Info for Event • BX/TURN BX & Turn Numbers • Header • P/N Some Trks w/ Pos/Neg Pt • Ntrk-Ptx No. of Trks in Pt Bin x • Data • S Sign of Trk • Pt Bin Pt Bin Number (0-3) • Pt Ext. Bin-1 (1.5-3 GeV) A-Offset Bin-2 (3-5 GeV) A-Offset Bin-3 (5-10 GeV) Pt-Info Bin-4 (10- GeV) Pt-Info • Error Transmission Errors • Rel  H-Layer Fiber Number (0-43) • D Track also sent to Adjacent Segm • Trk Adr Address of 4.5o wedge of Trk STT Review: 25-Feb-00

  9. Buffer Management Buffer Manager SLVRDY* VBD SCL DONE* Msg status start-mon CPU VBDbusy Local Buffer Controller mon-done Functions • Manage List of W/R Buffer No.’s for Entire System • Broadcast next W/R Buffer No. based on SCL Info • Receive Status Info from All Boards • Signal VBD to begin Reading Buffers • Signal CPU to begin Monitoring • Arbitrate VME bus between VBD and CPU • Broadcast SCL Init to Entire System • Receive Init Status from other boards • Send Init Status to SLCF  SCL Hub STT Review: 25-Feb-00

  10. Buffer Allocation available buffer numbers used buffer numbers L2_REJECT L1_PERIOD L2_ACCEPT enable enable SCAN_READY L2_PERIOD Write Buffer No. Read Buffer No. STT Review: 25-Feb-00

  11. BM – Messages/Status Status Lines are ORed on Backplane STT Review: 25-Feb-00

  12. Local Buffer Controllers Xmit Logic scan busy * Out FIFO Buffers VME Rcv Logic Buffer Control r/o busy * BC FIFO In FIFO message status Data In: PCI J3 Buffer Manager DB Data Control STT Review: 25-Feb-00

  13. SCL Init SCL Hub (via SCL mezz) SCL_INIT Buffer Manager SCL Formatter SCL_INIT INIT_ACK INIT_ACK RESET_DONE (stat-i) FRC DB DB Init AckOR RESET (mess-13,14) RESET_DONE[n] STT Board n RESET_DONE[1] STT Board 1 STT Board 0 RESET_DONE[0] Local Buffer Ctrl Board 0 DB DB Global Ctrl Reg DB Global Stat Reg Elem Init Ack Logic DB Elem-1 Ctrl Reg DB Elem-1 Stat Reg DB Elem-2 Ctrl Reg DB Elem-2 Stat Reg DB Elem-1 (RR) DB Elem-1 (TRDF) No Data Clear Inputs Clear Inputs No Data STT Review: 25-Feb-00

  14. Testing/Monitoring Monitoring • FRC Monitoring Data Size Small • Provide 256 Byte Monitoring Register for each element Testing • Simulated Data Flow Test • Require ability to load several events of data at each element in FRC • Small FIFOs (Data Register) STT Review: 25-Feb-00

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