An Improved “Soft” eFPGA Design and Implementation Strategy

1. An Improved “Soft” eFPGA Design and Implementation Strategy Victor Aken’Ova, Guy Lemieux, Resve Saleh SoC Research Lab, University of British Columbia Vancouver, BC Canada

2. Overview • Introduction and Motivation • Embedded FPGA (eFPGA) • Soft Embedded FPGAs • Configurable Architecture • Improving Soft eFPGAs • Tactical Standard Cells • Structured eFPGA layout • Results • Summary and Conclusions

3. eFPGAs Introduction • SoC designs are getting more complex and costly • Programmability can be built into SoCs to amortize costs by reducing chip re-spins Software Flexibility No Flexibility Hardware Flexibility

4. CPU Applications for eFPGA Fabrics An eFPGA for CPU acceleration 3 1 2 eFPGA for product differentiation An eFPGA for revisions

5. Motivation • shortcomings of existing eFPGA design approaches • Hard eFPGA • Highly efficient full-custom layouts but inflexible • Soft eFPGA • Very flexible but inefficient standard cell layouts • alternative approach: flexible + efficient

6. ? ? ? Restrictive! overcapacity increases area and delay overheads “Hard” eFPGA Approach with a library of 3 Cores user circuit 1 RTL 3 2

7. auto generated eFPGA much less logic and routing overcapacity 7x area and 2x delay versus full-custom The “Soft” eFPGA Approach eFPGA RTL Generator ASIC flow Generic Standard Cells

8. use structured approach for efficiency • use tactical cells to reduce area + delay Some Solutions to Problems of Existing Approaches • retain eFPGA generator idea for flexibility But…

9. Our Improved Design Approach“Soft++” eFPGA RTL Generator auto generated eFPGA Structured ASIC FLOW GOAL Tactical +Generic Cells combine best of soft and hard approaches

10. Island-style eFPGA Architecture • used island-style architecture because • Mainstream: existing FPGA CAD tools can can be leveraged • can exploit its regular structure to improve design efficiency • Created parameterized eFPGA in VHDL

11. L: Left Edge TILE B: Bottom Edge TILE C: Corner TILE L B C Island-style eFPGA Architecture (b) eFPGA Tile Layout (a) Island-style eFPGA

12. Fixed Logic Fixed Logic Soft eFPGA Unstructured vs. Structured eFPGA Design Approach tile1 tile2 tile4 tile3 (a) unstructured eFPGA layout (b) structured eFPGA layout

13. Measured Impact of Structure on eFPGA Quality • Significant improvements in logic capacity • result of a more efficient CAD methodology • wire-only critical path delay less by 21% • Cut CAD design time by as much as 6X

14. Architecture-specific Tactical Cells – The Concept • improve quality by creating few tactical standard cells to replace generic cells • detailed analysis of design profile should reveal areas that yield significant gains

15. Standard cell Area Breakdown for Island-Style Architecture switch 16% other 12% LUT 30% input mux 13% muxes 42% flip-flops 46% LUT mux 39% flip-flops and multiplexers dominate eFPGA area

16. Architecture-specific Tactical Cells – Flip-Flop vs. SRAM ~2:1 area ratio! (a) typical D flip-flop (b) typical SRAM cell An SRAM circuit has fewer transistors = less area

17. vdd vdd 1X 2.5X gnd gnd Custom Layout of Standard Cell – Flip-Flop vs. SRAM Standard Cell Flip-flop Tactical SRAM Cell

18. A S0 VDD S1 S1 S0 S0 A B S1 O S0 B C S1 S0 O C D S0 D Architecture-specific Tactical Cells – CMOS vs. Pass Gate after extra output inverter decompose into NAND, INV ~4:1 area ratio! pass tree logic uses fewer transistors and is faster

19. Layout Technique for Pass-Tree Multiplexers vdd n-well n-well vdd n-well cutout gnd extra NMOS (denser cell) gnd underutilized region n-well cut-outs allow denser pass transistor tree layouts

20. Architecture-specific Tactical Cells – Cell Area Equivalent Standard cell Area (um2) Custom Tactical cell Area (um2) improvement Factor Cell 61 24 1-SRAM 2.5 899 6.1 146 16:1 MUX 2228 293 7.6 32:1 MUX 530 1875 3.5 4-LUT 3.9 1061 4180 5-LUT

21. -85% -58% eFPGA eFPGA Area Impact of Tactical Standard Cells – eFPGA Area eFPGA (a) soft (b) soft ++ (c) full-custom soft ++ ~2.4X smaller than soft = 58% area savings

22. Graphs of Area and Delay Savings 2.4X Better Area 1.6 – 2.8X full-custom area Benchmarks 1.4X Better Delay 1.1X of full-custom delay Benchmarks

23. Fabricated Chip Designs with eFPGAs (180nm process) (a) gradual architecture (b) island-style architecture

24. Summary • eFPGA area improved 58% (on average) • 2 to 2.8X larger than full-custom equivalent (worst case) • eFPGA delay improved 40% (average) • within 10% of delay of full-custom versions • exploited the regularity of island-style architecture to increase logic capacity

25. End of Talk

26. Soft++ Soft hard custom soft++ fills some of performance gap left by hard Question and Answer Slide Area Logic Capacity