Packet Classification on PLUG Architecture

1. Packet Classification on PLUG Architecture Nilay Vaish Thawan Kooburat CS/ECE 752 Advance Computer Architecture I Fall 2010

2. Motivation • Routers need packet classification to: • QoS, Security (Firewall), VPN, and etc. • Traffic volume increase rapidly • Traffic volume increasing rapidly • Reported CAGR of 50% during 2006 – 2010 • Classifier size also increase • Hardware support • TCAM – Fixed latency but high power consumption and cost • CPU – Maximum flexibility but with high power consumption • Custom logic – Good power efficiency but inflexible

3. Background: PLUG • Pipelined LookUp Grid (PLUG) • Tiled architecture • N cores, M memory, R router • Simple µcores • SRAM memory • Message routing via adjacent tile • RISC-like ISA with static scheduling • Data flow programming model Message Code block Data Code block Data Input Output Code block Code block

4. Background: EffiCuts Decision-tree packet classification algorithm Rule Space Rule A Rule B Rule C Rule C Rule D

5. Background: EffiCuts (cont.) Efficient memory usage: 855KB for 10k rule set Packet X,Y = (1,2) Node Boundary X = [0, 1] 2 cuts Y = [0, 3] 4 cuts Index = X-offset * (Y-cuts) + Y-offset= 1 x 4 + 2 = 6 Y Children Array X 0 1 2 3 4 5 6 6 7

6. Mapping EffiCuts to PLUG Input 1st level page 2rd level page 3rd level page 4th level page Leaf + rule array page Rule array Rule array Output

7. Memory Access Scheduling Periodic multiple accesses Complex multiple accesses m n m n m n m m m n n n m m m n n n m m m n n n Memory access Computation 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

8. Evaluation • Critical path length. • Child code block: 200 instructions (4 memory accesses) • Leaf code block: 150 instructions (10 memory access)

9. Questions Q/A