EECS 40 Spring 2003

1. Lecture 23 Computing Gate Delay 4/1/03 Prof. Andy Neureuther Discharging Capacitance through a MOS device? Equivalent resistance model for MOS CMOS Logic operation Path dependent delay Worst cae and Cascade EECS 40 Spring 2003

2. VDD p-type MOS Transistor (PMOS) VIN-U Output IOUT n-type MOS Transistor (NMOS) VOUT VIN-D Transient Gate Problem: Discharging and Charging Capacitance on the Output 5V => 0 VIN = VDD = 5V COUT = 50 fF

3. VOUT(0) = 5V IOUT-SAT-D = 100 mA 100 IOUT-SAT-D = 100 mA COUT = 50 fF 60 VIN = 5V IOUT(mA) 20 0 3 5 VOUT(V) Output Propagation Delay High to Low When VIN goes High VOUT starts decreases with time Assume that the necessary voltage swing to cause the next downstream gate to begin to switch is VDD/2 or 2.5V. That is the propagation delay tHL for the output to go from high to low is the time to go from VDD = 5V to to VDD/2 =2.5V

4. VOUT(0) = 5V IOUT-SAT-D = 100 mA 100 IOUT-SAT-D = 100 mA COUT = 50 fF 60 VIN = 5V IOUT(mA) 20 0 3 5 VOUT(V) Output Propagation Delay High to Low (Cont.) When VOUT > VOUT-SAT-D the available current is IOUT-SAT-D For this circuit when VOUT > VOUT-SAT-D the available current is constant at IOUT-SAT-D and the capacitor discharges. The propagation delay is thus

5. RD Switched Equivalent Resistance Model The above model assumes the device is an ideal constant current source. 1) This is not true below VOUT-SAT-D and leads to in accuracies. 2) Combining ideal current sources in networks with series and parallel connections is problematic. Instead define an equivalent resistance for the device by setting 0.69RDC equal to the Dt found above This gives Each device can now be replaced by this equivalent resistor.

6. VOUT(0) = 5V IOUT-SAT-D = 100 mA 100 IOUT-SAT-D = 100 mA COUT = 50 fF 60 VIN = 5V IOUT(mA) 20 0 3 5 VOUT(V) ¾ VDD/ISAT Physical Interpretation ¾ VDD is the average value of VOUT Approximate the NMOS device curve by a straight line from (0,0) to (IOUT-SAT-D, ¾ VDD ). Interpret the straight line as a resistor with 1/(slope) = R = ¾ VDD/ISAT

7. Switched Equivalent Resistance Values The resistor values depend on the properties of silicon, geometrical layout, design style and technology node. n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type. The resistance is inversely proportion to the gate width/length in the geometrical layout. Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size. The current per unit width of the gate increases nearly inversely with the linewidth. For convenience in EE 42 we assume RD = RU = 10 kW

8. VDD VDD RD VOUT VOUT VIN = Vdd VIN = Vdd COUT = 50fF COUT = 50fF Inverter Propagation Delay Discharge (pull-down) Dt = 0.69RDCOUT = 0.69(10kW)(50fF) = 345 ps Discharge (pull-up) Dt = 0.69RUCOUT = 0.69(10kW)(50fF) = 345 ps

9. VDD A C B VOUT B A C Logic is Complementary and produces F = A + (BC) CMOS Logic Gate NMOS and PMOS use the same set of input signals PMOS only in pull-up PMOS conduct when input is low PMOS do not conduct when A +(BC) NMOS only in pull-down NMOS conduct when input is high. NMOS conduct for A + (BC)

10. VDD A C B VOUT B A C CMOS Logic Gate: Example Inputs A = 0 PMOS all conduct B = 0 Output is High C = 0 = VDD NMOS do not conduct Logic is Complementary and produces F = 1

11. VDD A C B VOUT B A C CMOS Logic Gate: Example Inputs A = 0 PMOS A conducts; B and C Open B = 1 Output is Low C = 1 = 0 NMOS B and C conduct; A open Logic is Complementary and produces F = 0

12. VDD VDD A RD RU RU RU RD RD A C B VOUT C B VOUT B A B A C C Switched Equivalent Resistance Network Switches close when input is low. Switches close when input is high.

13. VDD A RD RU RU RU RD RD C B VOUT B A COUT = 50 fF C Logic Gate Propagation Delay: Initial State The initial state depends on the old (previous) inputs. Example: A=0, B=0, C=0 for a long time. These inputs provided a path to VDD for a long timeand the capacitor has precharged up to VDD = 5V.

14. VDD A RD RD RU RU RD RU This breaks the path from VOUT to VDD C B VOUT And opens apath from VOUT to GND B A COUT = 50 fF C Logic Gate Propagation Delay: Transient The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new present input state. Example: At t=0, B and C switch from low to high (VDD) and A remains low. COUT discharges through the pull-down resistance of gates B and C in series. Dt = 0.69(RDB+RDC)COUT = 0.69(20kW)(50fF) = 690 ps The propagation delay is two times longer than that for the inverter!

15. VDD RD RD RU RU RU RD A Fastest overall? C B VOUT Slowest overall? B COUT = 50 fF A C Logic Gate: Worst Case Scenarios What combination of previous and present logic inputs will make the Pull-Up the fastest? What combination of previous and present logic inputs will make the Pull-Up the slowest? What combination of previous and present logic inputs will make the Pull-Down the fastest? What combination of previous and present logic inputs will make the Pull-Down the slowest?

16. VDD B2 = VOUT 1 VDD A1 50 fF 50 fF A2 B1 VOUT 1 C2 B2 VOUT 2 B2 A1 B1 A2 C2 Logic Gate Cascade To avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks. The four independent input are A1, B1, A2 and C2. Fastest: A2 high discharges gate 2 without even waiting for the output of gate 1. Slowest: C2 high and A2 low makes gate 2 wait for Gate 1 output