POWER and ENERGY OPTIMIZATION

1. POWER and ENERGY OPTIMIZATION Muhammed İ. KALKAN 2007704323

2. Low Power Processor Design • Low power consumption is paramount in all types of processor-based embedded systems. • Battery-based portable systems require a low-power methodology. • Low power processor design includes gaining a thorough understanding of • How the application affects power, • Identifying power-hungry parts of the design and application, • Comparing configuration options

3. Low Power Processor Design • Processor power consumption as having two fundamental power components: • Static • Active • Static power is consumed when there is no CPU activity on the digital signal processor (DSP) or microcontroller (MCU). • For the most part, static power is determined by • Semiconductor process technology, • Processor core • I/O voltages • Device operating temperature.

4. Low Power Processor Design • Semiconductor vendors can minimize static power with process-oriented adjustments such as • Processes and transistors with low leakage currents • But there is a trade-off • Lower frequency ,lower processor performance.

5. Low Power Processor Design • Major contributors to active power • CPU voltage, • Frequency, • Activity, • Its peripherals activity • Off chip memory activity. • Various options on how a processor is used, system designers can optimize for low power operations by comparing different hardware and software configurations. • The process starts with estimating active power consumption under various scenarios, module by module.

6. Low Power Processor Design • The most common modules include • Clock generator • CPU • External memory interface (EMIF) • Direct memory access (DMA) interface or Host Processor Interface (HPI) • Multi-channel Bufferes Serial Ports (McBSPs) • Memory modules • SD card host controller • I2C interface • Timers • USB ports • Watchdog timer (WDT) • Analog-to-digital converter (ADC) • Real-time clock (RTC) • General purpose IO interface.

7. Low Power Processor Design • Utilizing Microcontroller Units to minimize power consumption and extend battery life is accomplished through architectural choices and software efficiency. • Methods for Utilizing Power Efficiency • System designers should take full advantage of MCUs with clock systems that allow several low-power operating modes but is still based on a single crystal.

8. Low Power Processor Design • A low-frequency auxiliary clock will enable ultra-low-power standby mode with real time clock functionality. • A faster, internal digitally-controlled oscillator (DCO) will allow the same crystal to source the master clock used by the CPU and high-speed peripherals, thus eliminating long start ups required when the MCU architecture includes two crystals or two-speed startup.

9. Low Power Processor Design • Using a faster clock while active allows applications to minimize the time they spend in an active mode, and can return to a lower power standby most as quickly as the task completes.

10. Low Power Processor Design • Avoid polling as it keeps the MCU and the system active more than is needed. • System designers should architect their products to be event-driven. • Waking the MCU only when it needs to do something is an important strategy in minimizing active power consumption.

11. Low Power Processor Design • Design the system with external devices that can be shut down or turned off. • With low duty cycle applications, this will lower total system power consumption over the operating life of an application compared to using conventional low power devices that are always on.

12. Low Power Processor Design • Terminate unused pins because floating inputs are responsible for significant power loss • Integrating peripherals into the MCU is more energy efficient than using discrete parts. • Intelligent peripherals can offload the CPU so that it does not need to be over-clocked to deliver the required system performance. • Many MCUs allow the system to stay in a low power mode with the CPU off but still allows system clocks to trigger integrated peripherals.

13. Low Power Processor Design • Another way to reduce energy consumption: • Write code that minimizes the number of clock cycles required for executing a command. • Every instruction executed consumes a portion of the battery that will never come back. • Code should be written to minimize the amount of memory in use at any time.

14. Low Power Processor Design • Random memory location can be addressed and operated on directly • This approach requires both an additional memory word and cycle. • Write instructions that use CPU registers • They require only one clock cycle and one word of code space. • Using CPU registers for dedicated variables will also reduce code size and increase execution speed.

15. Low Power Processor Design • On 16-bit architectures: • Addressing either words or bytes requires the same amount of code and cycles • Operate on words when possible to reduce code size and increase execution speed. • If the MCU supports a constant generator, be sure to utilize it.

16. Low Power Processor Design • Constant generators automatically generate the most frequently used immediate constants in hardware. • Power reduction occuresif a dedicated CPU register is used automatically for constant generation. • No operand is fetched from memory, saving code and increasing speed.

17. Low Power Processor Design • Other ways to save power • Use local variables as much as possible because the CPU registers instead of the RAM used by global variables • Use bit mask instead of bitfields for unsigned int and unsigned char • Use unsigned data types when possible • Use pointers to access structures and unions • Use "static const" class to avoid run-time copying of structures, unions and arrays • Avoid modulo.

18. Low Power Processor Design • Split-rail design: • Allows lower voltages to be used in the processor core while the external Input/Output (I/O) voltages remain 3.3 volts for backwards compatibility. • Dual-voltage CPUs were introduced for performance gain when increasing clock speeds and finer semiconductor fabrication processes resulted in excess heat generation and power supply concerns, especially regarding laptop computers. • Using a voltage regulator, the external I/O voltage levels would be transformed to lower voltages in order to reduce power usage, resulting in less heat being produced with the ability to operate at higher frequencies.

19. Low Power Processor Design • Dynamic Voltage Scaling: • Dynamic voltage scaling is a power management technique in computer architecture. • The voltage used in a component is increased or decreased, depending upon circumstances • Dynamic voltage scaling to decrease voltage is known as undervolting. • Undervolting is done in order to conserve power, particularly in laptops and other mobile devices, where energy comes from a battery and thus is limited. • Overvolting is done in order to increase computer performance.

20. Digital Voltage Scaling Loop • The feedback loop for converting a desired operating frequency

21. Low Power Processor Design • Dynamic Frequency Scaling: • Technique in computer architecture where a processor is run at a less-than-maximum frequency in order to conserve power. • As frequency changes, the dynamic power will change linearly with it. • Dynamic power does not account the total power of the chip • There is also static power, which is primarily due to various leakage currents

22. Low Power Processor Design • Leakage Current: • Gradual loss of energy from a charged capacitor. • It is primarily caused by electronic devices attached to the capacitors, such as transistors or diodes, which conduct a small amount of current even when they are turned off. • Even though this off current is an order of magnitude less than the current through the device when it is on, the current still slowly discharges the capacitor.

23. Low Power Processor Design • Clock Gating: • One of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor. • In order to save power, clock gating support adds additional logic to a circuit to prune the clock tree, • Disabling portions of the circuitry so that its flip-flops do not change state • Their switching power consumption goes to zero, and only leakage currents are incurred.

24. Low Power Processor Design • Prone the idle parts

25. Low Power Processor Design • A Study for Low Power CPU Design (Briefly) • As clock frequency increases and feature size decreases,clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. • An alternative approach, which is called a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be performed.

26. Low Power Processor Design • In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. • An MCD microprocessor affords a number of potential advantages over a singly clocked design:

27. Low Power Processor Design • The global clock distribution network is greatly simplified,requiring only the distribution of the externally generated clock • The designers of each domain are no longer constrained by the speeds of critical paths in other domains, • Greater freedom in each domain to optimize the tradeoffs among clock speed, latency, and the exploitation of application parallelism via complex hardware structures.

28. Low Power Processor Design • Using separate voltage inputs, external voltage regulators, and controllable clock frequency circuits in each clock domain allows for finer grained dynamic voltage and frequency scaling, • Allows lower energy, than can be achieved with single clock, single-core-voltage systems.

29. Low Power Processor Design

30. Low Power Processor Design • Division of Chip into Clock Domains • Design uses four domains, one of which includes the L2 cache, so that domains may vary somewhat in size and still be covered by a single clock. • No energy savings from decoupling instruction fetch from rename/dispatch, • Combine these regions into a single fetch/rename/dispatch domain to eliminate their interdomain synchronization overhead.

31. Low Power Processor Design • Execution units of the same type (e.g., integer units) were combined into a single domain to avoid the high cost of synchronizing the bypass and register file datapaths among these units. • Inter Domain Synchronization • Synchronizing the modules seperated

32. Low Power Processor Design • Work concludes • Multiple clock domain (MCD) microarchitecture, which uses a globally asynchronous, locally-synchronous (GALS) clocking style • With dynamic voltage and frequency scaling in order to maximize performance and energy efficiency for a given application.

33. Low Power Processor Design • Scaling frequency and voltage in different domains dynamically and independently • Can achieve an average improvement in energy-delay product of nearly 20% • On the other hand, global voltage scaling to achieve comparable performance degradation in a singly clocked microprocessor achieves an average energy-delay improvement of only 3%.

34. References • http://en.wikipedia.org/wiki/Dynamic_voltage_scaling • Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, and Michael L. Scott • http://en.wikipedia.org/wiki/Dual-voltage_CPU • LOW-POWER PROCESSOR DESIGN,Ricardo E. Gonzalez • http://en.wikipedia.org/wiki/Dynamic_frequency_scaling • http://www.automotivedesignline.com/212200726?cid=RSSfeed_automotivedesignline_adlRSS • http://en.wikipedia.org/wiki/Dual-voltage_CPU • http://www.powermanagementdesignline.com/howto/batterymanagement/212100642