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ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Transistor Sizing. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University
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ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsDynamic Power: Transistor Sizing Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC5970-001/6970-001 Lecture 7
Cg Delay of a CMOS Gate Intrinsic capacitance Gate capacitance CMOS gate Cint CL Propagation delay through the gate: tp = 0.69 Req(Cint + CL) ≈ 0.69 ReqCg(1 + CL /Cg) = tp0(1 + CL/Cg) ELEC5970-001/6970-001 Lecture 7
Req, Cg, Cint, andWidth Sizing • Req: equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor • Cg: gate capacitance, proportional to CoxWL; scales as S • Cint: intrinsic output capacitance ≈ Cg, for submicron processes • tp0: intrinsic delay = 0.69ReqCg; independent of sizing ELEC5970-001/6970-001 Lecture 7
Effective Fan-out, f • Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f = CL/Cg tp = tp0(1 + f ) ELEC5970-001/6970-001 Lecture 7
Cg1 Cg2 Sizing an Inverter Chain 1 2 N CL Cg2 = f2Cg1 tp1 = tp0 (1 + Cg2/Cg1) tp2 = tp0 (1 + Cg3/Cg2) N N tp = Σtpj = tp0Σ (1 + Cgj+1/Cgj) j=1j=1 ELEC5970-001/6970-001 Lecture 7
Minimum Delay Sizing Equate partial derivatives of tp with respect to Cgj to 0: 1/Cg1 – Cg3/Cg22 = 0, etc. Cg22 = Cg1×Cg3, etc. Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N) ELEC5970-001/6970-001 Lecture 7
Minimum Delay Sizing Equate partial derivatives of tp with respect to N to 0: dNtp0(1 + F1/N) ───────── = 0 dN i.e. F1/N – F1/N(ln F)/N = 0 or ln f = 1 → f = e = 2.7 and N = ln F ELEC5970-001/6970-001 Lecture 7
Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC5970-001/6970-001 Lecture 7
CL Cg1 Sizing for Energy Minimization f 1 tp = tp0 [(1+f) + (1+F/f )] = tp0(2+ f + F/f ) F = CL/Cg1 tp0 ~ VDD/(VDD - Vt) Energy dissipation, E = VDD2Cg1(1 + f + F ) ELEC5970-001/6970-001 Lecture 7
Holding Delay Constant • Reference circuit: f = 1, supply voltage = Vref • Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: tp tp0(2+f+F/f ) VDD Vref -Vt 2+f+F/f ── = ──────── = ── ──── ───── ≤ 1 tpref tp0ref (3+F ) Vref VDD -Vt 3+F ELEC5970-001/6970-001 Lecture 7
Supply Voltage Vs. Sizing 3.5 3.0 2.5 2.0 1.5 1.0 Vref = 2.5V Vt= 0.5V F=1 2 5 fopt ≈ √F VDD (volts) 10 1 2 3 4 5 6 f ELEC5970-001/6970-001 Lecture 7
Energy E VDD22 + 2f + F ── = ─── ────── Eref Vref2 4 + F ELEC5970-001/6970-001 Lecture 7
Normalized Energy Vs. Sizing 1.5 1.0 0.5 Vref = 2.5V Vt = 0.5V F=1 2 5 fopt≈ √F Normalized Energy 10 1 2 3 4 5 6 f ELEC5970-001/6970-001 Lecture 7
Summary • Device sizing combined with supply voltage reduction reduces energy consumption. • For large fan-out energy reduction by a factor of 10 is possible. • An exception is F = 1 case, where the minimum size device is also the most effective one. • Oversizing the devices increases energy consumption. ELEC5970-001/6970-001 Lecture 7
