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ARM Tachnology

ARM Tachnology. Chapter 3. STM32 Clock and Configuration. CONTENTS. Objectives Clock System of STM32F103 Clock Configuration of STM32 STM32 functions related to clock. 3.1 Objectives.

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ARM Tachnology

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  1. ARM Tachnology

  2. Chapter 3 STM32 Clock and Configuration

  3. CONTENTS Objectives Clock System of STM32F103 Clock Configuration of STM32 STM32 functions related to clock

  4. 3.1 Objectives All STM32 peripherals are driven by the clock, and every module uses independent clock to meet the low-power requirement. So STM32 clock system must be studied in detail to use peripherals properly.

  5. 3.2 STM32 Clock System There 5 clock sources in STM32F103：HSI (High Speed Internal)HSE (High Speed External) LSI (Low Speed Internal) LSE (Low Speed External) PLL(Phase Locked Loop) Where, HIS, HSE, and PLL can be used as System Clock.LSI and LSE are second level clock. The clock tree of STM32F103 is shown in Fig.11 on page 115 of the STM32 Reference Manual (RM)

  6. The clock tree of STM32F103 is shown in Fig.11 on page 115 of the STM32 Reference Manual (RM)

  7. There are several clocks for MCU core and different peripherals. Why?

  8. First reason High speed clock is used for high speed devices, like CPU, and low speed clock is used for low speed devices like peripherals. Second reason This mode of clock is helpful to realize low power.

  9. Enable clock out Due to the requirement of low power, every module of STM32 microcontroller uses the clocks independently. So, when we use a peripheral, we must enable its clock firstly. Otherwise, it will not work.

  10. 3.3 Clock configuration of STM32 In general, an embedded system should be initialized before it works. In embedded system initialization, the system should be set up. The clock source should be considered in clock setup, and PLL should also be considered. Then the internal bus, external bus and peripherals clock should be set up. The flow chart of clock setup is shown in Fig.3-1. Fig. 3-1 Flow chart of clock setup

  11. The reset and clock setup of STM32F103 include 10 registers: ①Clock control register (RCC_CR) ②Clock configuration register (RCC_CFGR) ③Clock interrupt register (RCC_CIR) ④APB2 peripheral reset register (RCC_APB2RSTR) ⑤APB1 peripheral reset register (RCC_APB1RSTR) ⑥AHB Peripheral Clock enable register (RCC_AHBENR) ⑦APB2 peripheral clock enable register(RCC_APB2ENR) ⑧APB1 peripheral clock enable register(RCC_APB1ENR) ⑨Backup domain control register (RCC_BDCR) ⑩Control/statusregister (RCC_CSR) They can be viewed in STM32 Reference Manual (RM) from page 121 ‘7.3 RCC registers’

  12. 1. Reset and Clock Configuration Registers The clock setup starts with RCC（Reset and Clock Configuration. In firmware library, RCC registers are defined using structure RCC_TypeDef. In stm32f10x_map.h, it is defined as following: /*------------------------ Real-Time Clock -----------------------------------*/ typedef struct { vu32 CR; vu32 CFGR; vu32 CIR; vu32 APB2RSTR; vu32 APB1RSTR; vu32 AHBENR; vu32 APB2ENR; vu32 APB1ENR; vu32 BDCR; vu32 CSR; } RCC_TypeDef;

  13. /* Peripheral base address in the bit-band region */ #define PERIPH_BASE ((u32)0x40000000) /* Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x1 0000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x2 0000) #define RCC_BASE (AHBPERIPH_BASE + 0x1000) #ifdef _RCC #define RCC ((RCC_TypeDef *) RCC_BASE) #endif /*_RCC */ Pay attention to the Macro definition. RCC in the programs will be replaced with ((RCC_TypeDef *) 0x40021000) 

  14. 2. ErrorStatus In stm32f10x_type.h, ErrorStatus is defined as following: typedef enum {ERROR=0, SUCCESS=! ERROR} ErrorStatus; 

  15. 3.4 STM32 functions related to clock 1. SystemInit SystemInit is called before main function. And it is called in startup file to system reset and clock initialization. void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ RCC->CR |= (uint32_t)0x00000001; /* Set HSION bit 内部高速时钟使能*/ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF;

  16. /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */

  17. #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif }

  18. 2. RCC_Configuration ErrorStatus HSEStartUpStatus; void RCC_Configuration(void) { /*set RCC registers to default valuesRCC system reset*/ RCC_DeInit(); /*Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /*Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) // SUCCESS { /*AHB= SYSCLK= 48 MHz, HCLK(AHB clock) = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /*PCLK2(APB2 clock)= AHB clock/2 = 24 MHz，PCLK2 = HCLK/2 */ RCC_PCLK2Config(RCC_HCLK_Div2);

  19. /*PCLK1(APB1 clock)= AHB clock/4=12MHz, PCLK1 = HCLK/4 */ RCC_PCLK1Config(RCC_HCLK_Div4); //RCC_HCLK_Div4: APB1 clock = HCLK/4=12MHz /* set Flash delay clocks to 2 */ FLASH_SetLatency(FLASH_Latency_2); /* Enable FlashPrefetch Buffer*/ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* PLLCLK = 8MHz * 6 = 48 MHz */ RCC_PLLConfig ( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6); /* Enable PLL */ RCC_PLLCmd(ENABLE);

  20. /* Wait till PLL is ready*/ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ //Select PLLCLK as SYSCLK RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /*Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } /* Enable peripheral clocks --------------------------------------------------*/ /* GPIOA, GPIOB and SPI1 clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_SPI1, ENABLE); /* Enable GPIOC, GPIOD clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC| RCC_APB2Periph_GPIOD, ENABLE); }

  21. 3. Enable clocks of peripherals connected to APB1 BUS RCC_APB1PeriphClockCmd( ) For example, the following function is used to enable the TIM2 clock: RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2，ENABLE); 4. Enable clocks of peripherals connected to APB2 BUS RCC_APB2PeriphClockCmd( ) For example, the following function is used to enable clocks of GPIOB and GPIOE: RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOE，ENABLE);

  22. 5. Enable clocks of peripherals connected to AHB BUS RCC_AHBPeriphClockCmd( ) 函数 For example, the following function is used to enabl DMA clock: RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA，ENABLE);

  23. All the functions above can be found in ‘stm32f10x_rcc.h’ and ‘stm32f10x_rcc.c’.

  24. The clock tree of STM32F103 and clock configuration are discussed in this part. These contents are very important to develop STM32 based system.

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