Memory Organization and Architecture - Enhancing Memory Operations

1. CHAPTER 4 Memory System Organization and Architecture -MEMORY ENHANCEMENT

2. Memory operation (read / write) • The processor needs to read data from memory and write data to memory. This requires the use of: • Bus – address bus, data bus and control bus • Memory Address Register (MAR) • Memory Data Register/Memory Buffer Register (MDR/MBR)

3. Memory Address Register (MAR) • Holds the address in the memory that is to be “opened” for data • Connected to a decoder that interprets the address and activate a single address line into the memory.

4. Memory Data Register (MDR) • Connected to every cell in the memory unit • Each bit of the MDR is connected in a column to the corresponding bit of every location in memory (but only a single row of cells is activated at any given time, thus, only one memory location is addressed at any one time)

6. Read Operation • CPU copies an address from some register in the CPU to the memory address register (MAR) • At the same time, the CPU sends a message to the memory unit that the memory transfer is retrieval (READ) from memory • CPU then momentarily turns on the switch that connects the MDR with the register, and transfer takes place between MDR and memory

7. The data will then be transferred to the appropriate register in the CPU • Memory content will remain intact while the content of MDR will be replaced by the new data from memory

8. Write operation • CPU copies an address from some register in the CPU to the memory address register (MAR) • At the same time, the CPU sends a message to the memory unit that the memory transfer is store (WRITE) to memory. • CPU then momentarily turns on the switch that connects the MDR with the register, and data transfer takes place between the register and MDR.

9. The data will then be transferred from the MDR to the memory location as specified in the MAR.

10. Memory Enhancement • Method to improved memory accesses: • Wide path Memory Access • Memory Interleaving • Cache Memory

11. Wide Path Memory Access • Widen the data path to read/write several bytes/words between the CPU and memory for each access • Retrieve multiple bytes instead of 1 byte at a time • Using larger memory data register

12. Memory Interleaving • Divide memory into parts • Partition memory into subsections, each with its own address register and data register

14. Cache Memory • Position a small amount of high speed memory • Organized into blocks • Each block provides a small amount of storage

16. Virtual Storage • Increases the apparent amount of memory by using far less expensive hard disk space • look at RAM for areas that have not been used recently and copy them onto the hard disk • This frees up space in RAM to load the new application. • Implemented through paging: • Demand paging • Page reside on hard disk and are brought into memory as needed • Page table • Keeps track of what is still out on hard disk • Inverted page table • Representation of physical memory with the page that resides in each frame

17. Advantages • Programs share memory space • More programs run at the same time • Programs run even if they cannot fit into memory all at once

18. Disadvantages • SWAP file takes up space on disk • Paging takes up resources of the CPU