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Engineering Technology. State Machines in VHDL. Dr. H.v.d.Biggelaar March 22, 2000. State Machines. Moore. Mealy. similarities between the clocking of a bank of flip-flops and the flip-flops in a state machine.
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Engineering Technology State Machines in VHDL Dr. H.v.d.Biggelaar March 22, 2000 Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State Machines Moore Mealy Dr. H.v.d.Biggelaar / Mar3-Ver2 /
similarities between the clocking of a bank of flip-flops and the flip-flops in a state machine Dr. H.v.d.Biggelaar / Mar3-Ver2 /
An example of an FSM used as a controller for two counters Dr. H.v.d.Biggelaar / Mar3-Ver2 /
case ps is when s0 => if x='1' then ns<=s0; else ns<=s1; end if; when s1 => if x='0 then ns<=s1; else ns<=s2; end if; when s2 => ns<=s0; when others => ns<=s0; end case; Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Data Types Enumerated (user-defined): This is a list of values generated by the designer. Their synthesis is application-specific. The values of the elements in the list start at ‘0’ at the left “(“ and increment by one from there. Particularly useful in state machines. Example: type states is (idle, detect, send, receive); signal prsnt, next: states; Note: “Boolean” and “bit” are also enumerated types, defined by the IEEE standard. type Boolean is (false, true); type bit is (‘0’, ‘1’); Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State machines • Moore Machines A finite state machine in which the outputs change only due to a change of state • Mealy Machines A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State Output Logic Registers Moore state machine implementations (1) • Outputs decoded from state bits • Combinatorial decode Outputs are decoded combinatorially from the current state outputscomb = f(present state) Outputs Logic Inputs Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State Registers Output Output Logic Registers Moore state machine implementations (2) • Outputs decoded from state bits • Registered decode • Outputs are registered; decode of outputs is in parallel with decode of next state • outputsreg = f(previous state, inputs) Current State Next State Logic Inputs Outputs Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State Registers Moore State Machine Implementations (3) • Outputs encoded within state bits Example: State Output 1 Output 2 State Encoding s1 0 0 00 s2 1 0 01 s3 0 1 10 Note: Both bits of the state encoding are used as outputs Outputs Logic Inputs Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Complete code for a Moore machine with outputs q1 and q0 that reflect the value of the state variable. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Complete code for the same Moore machine as in the previous example, but with a single process. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
One-Hot Encoding One state per flip-flop: in FPGA-type architectures • reduces the next state logic • requires fewer levels of logic cells • enables high-speed state machines (> 100MHz). in CPLD-type architectures • reduces the number of product terms • can eliminate ‘expander’ product terms (i.e. reduce delays, and increase operating speed). • but, uses more macrocells and there may not be enough Flip-Flops Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Note that the values of the constants are chosen by the designer and thus are not limited to a “one-hot” sequence. For instance to minimize power, one may prefer a Gray code. Again the same Moore machine but this time with “one-hot” encoding Dr. H.v.d.Biggelaar / Mar3-Ver2 /
State Registers Mealy Machines • Outputs may change with a change of state OR with a change of inputs. Mealy outputs are non-registered because they are functions of the present inputs Outputs Logic Inputs Dr. H.v.d.Biggelaar / Mar3-Ver2 /
ASM chart of a Mealy machine The only output “z” is ‘1’ when the machine is in state “s1” AND the input “x” is ‘1’. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Complete code for a Mealy machine with only a conditional output. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
This simulation is not very useful. It does not show how “z” depends on the input “x” and the state. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
The same Mealy machine but with output “q” added to show the value of the state variable. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
This simulation is better. It’s clear now that “z” is a ‘1’ only when “x” is a ‘1’ AND the FSM is in state s1. However, the transitions of “x” take place only on the active edge of the clock, so you cannot tell if the response to the change in “x” is synchronous or asynchronous. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
By just moving the transition of “x’ from coinciding with a leading edge of the clock to a level portion, it becomes obvious that when “x” goes from ‘1’ to ‘0’, the output “z” changes immediately, so that action is asynchronous. Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Do you really want to do this? Dr. H.v.d.Biggelaar / Mar3-Ver2 /
ROM-Centered Design top entity outputs inputs ROM reg cen clock Dr. H.v.d.Biggelaar / Mar3-Ver2 /
ROM-Centered Design fsmrom ack pwait a(0) d(0) ret a(1) req d(1) ROM16x4 a(2) d(2) a(3) d(3) q0_i q1_i d0_i d1_i q1 d1 d0 q0 reg2 reset rst clk clock Dr. H.v.d.Biggelaar / Mar3-Ver2 /
Example: for addr = 0, the data is “0110” (B-A-ret-ack) or 6 (hex) Dr. H.v.d.Biggelaar / Mar3-Ver2 /
And that’s IT for State Machines Dr. H.v.d.Biggelaar / Mar3-Ver2 /
