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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. Tod Dickson University of Toronto June 9, 2005. Motivation. Ever-growing bandwidth demands results in higher data rate broadband transceivers Next generation wireline applications will exceed 80-Gb/s.
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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS Tod Dickson University of Toronto June 9, 2005
Motivation • Ever-growing bandwidth demands results in higher data rate broadband transceivers • Next generation wireline applications will exceed 80-Gb/s. • To date, serial transmitters at this data rate have not been demonstrated. • High power consumption even an 40-Gb/s makes high levels of integration difficult. • Reducing power consumption without sacrificing speed is a key challenge.
BiCMOS Cascode HBT vs. MOS High-Speed Logic • High speed due to intrinsic slew rate • Requires high supply voltage (3.3V or more) Lower supply voltage Needs higher current for same speed No power savings
BiCMOS logic family reduces supply voltage Reduce tail current with inductive peaking CLDV2 LP = 3.1 IT2 10 mm Stacked inductors Power reduction techniques 43-Gb/s latch consumes only 20mW
40-GHz PLL Output Driver On-chip PRBS for BIST 8:1 MUX 2.5-V, 10.7-to-86-Gb/s Serial Transmitter
1.5mm 1.8mm Die Photo & Measured Results • Measured 86-Gb/s eye diagram • 2 x 275mVpp output swing • < 600fs rms jitter • 6ps rise/fall times (20%-80%) Fabricated in 130-nm SiGe BiCMOS w/ HBT fT = 150 GHz
Conclusions • Demonstrated the first serial transmitter above 40-Gb/s in any semiconductor technology. • Low-power operation achieved by • employing BiCMOS high-speed logic family to reduce supply voltage. • trading off bias current for inductive peaking. • Adding a SiGe HBT to a CMOS process can result in a serial transmitter with twice the data rate and half the power dissipation.