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Circuits and Interconnects In Aggressively Scaled CMOS

Explore VLSI scaling in digital CMOS design, focusing on dynamic and static CMOS forms, gate performance predictions, circuit power management, voltage scaling, and architecture scaling. Understand the impact on wire resistance, capacitance, clock frequency, and gate efficiency. Learn key strategies for optimizing power, performance, and complexity in future chip designs.

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Circuits and Interconnects In Aggressively Scaled CMOS

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  1. Circuits and InterconnectsIn Aggressively Scaled CMOS Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu VLSI Scaling

  2. Device Scaling In digital CMOS design: • Only two circuit forms matter • (maybe three) • Static CMOS, and Dynamic CMOS These forms are used because: • They don’t demand much from devices • So they work with crummy transistors • Robust, especially static circuits VLSI Scaling

  3. 0.36 * Ldrawn 7 5 FO4 delay (nS) 3 1 2 1.5 1 0.5 0 Feature size (mm) FO4 Inverter Delay Under Scaling • Device performance will scale • FO4 delay has been linear with tech Approximately 0.36 nS/mm*Ldrawn at TT (0.5nS/mm under worst-case conditions) • Easy to predict gate performance • We can measure them • Labs have built 0.04mm devices • Key issue is voltage scaling VLSI Scaling

  4. Circuit Power • Is very much tied to voltage scaling • If the power supply scales with technology For a fixed complexity circuit • Power scales down as a^3 if you run as same frequency • Power scales down as a^2 if you run it 1/ a times faster • Power scaling is a problem because • Freq has been scaling at faster than 1/ a • Complexity of machine has been growing • This will continue to be an issue in future chips • Remember scaling the technology makes a chip lower power! VLSI Scaling

  5. Voltage Scaling • Circuits performance depends on the Vdd to Vth ratio • Ideally both should scale together • If Vth scales leakage scales • If Vth does not scale, gates get slower, or Vdd can’t scale as fast and power goes up • Leakage is easier to deal with than power, transistors will leak VLSI Scaling

  6. Semi-global wire resistance, 1mm long Semi-global wire capacitance, 1mm long Aggressive scaling Aggressive scaling 0.4 0.6 Conservative scaling Conservative scaling 0.3 0.4 Kohms pF 0.2 0.2 0.1 0 0 0.25 0.18 0.13 0.1 0.07 0.05 0.035 0.25 0.18 0.13 0.1 0.07 0.05 0.035 Technology Ldrawn (um) Technology Ldrawn (um) Scaling Global Wires • R gets quite a bit worse with scaling; C basically constant VLSI Scaling

  7. Semi-global wire resistance, scaled length Semi-global wire capacitance, scaled length Aggressive scaling Aggressive scaling 0.4 0.6 Conservative scaling Conservative scaling 0.3 0.4 Kohms pF 0.2 0.2 0.1 0 0 0.25 0.18 0.13 0.1 0.07 0.05 0.035 0.25 0.18 0.13 0.1 0.07 0.05 0.035 Technology Ldrawn (um) Technology Ldrawn (um) Scaling Module Wires • R is basically constant, and C falls linearly with scaling VLSI Scaling

  8. Architecture Scaling • Plot of IPC • Compiler + IPC • 1.5x / generation • What next? • Wider machines • Threads • Speculation • Guess answers to create parallelism • Have high wire costs • Won’t be easy VLSI Scaling

  9. Clock Frequency • Most of performance comes from clock scaling • Clock frequency double each generation • Two factors contribute: technology (1.4x/gen), circuit design VLSI Scaling

  10. Clock speed has been scaling faster than base technology Number of FO4 delays in a cycle has been falling Number of gates decrease 1.4x each generation Caused by: Faster circuit families (dynamic logic) Better optimization Approaching a limit: <16 FO4 is hard < 8 FO4 is very hard Gates Per Clock VLSI Scaling

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