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A New SCV Compliant Transaction Recording Monitor for the SystemC OCP Channel. Tim Kogel, OCP-IP Pavilion, DATE 2005. Outline. Motivation Introduction SystemC based Transaction Level Modeling SCV Transaction Recording OCP Transaction Recording Monitor Examples Channel Monitor
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A New SCV Compliant Transaction Recording Monitor for the SystemC OCP Channel Tim Kogel, OCP-IP Pavilion, DATE 2005
Outline • Motivation • Introduction • SystemC based Transaction Level Modeling • SCV Transaction Recording • OCP Transaction Recording Monitor • Examples • Channel Monitor • System Monitor • Outlook • Architects View Methodology and Coding Guidelines
MP-SoC Design Challenge Application Task 7 Task 2 Task 4 Task 6 Task 1 Task 3 Task 5 Task 8 Memory Spatial & TemporalMapping Multi-Processor System-on-Chip NoC IP IP C IP Mem IP
OCP-IP System Level Design WG Charter • TLM modeling of OCP • work on standards proliferation • improve specification by using ESL • metrics/goals • up-to-date SystemC modeling library available • improved time-to-market through streamlined ESL • adoption of OCP ESL methodology and tooling
Transaction Arbitration Memory Access ReqTrf B_REQ Grant Trf B_GRANT pins ReqRdTrf ADDR RD_REQ TLM module TLM module WR_REQ TryRd Trf DATA port i/f RDY Transaction Level Modeling RTL module RTL module TLM = no pins
packets TL3 causality, determinism, total event ordering functional specification, explicit communication burst of words TL2 realistic delay annotations architecture exploration, temporal & spatial mapping word cycle accurate TL1 100% cycle accurate performance profiling Abstraction Levels Communication Accuracy Data Accuracy Timing Accuracy Addressed Design Problems domain specific MoC tokens causality, partial event ordering algorithm design TLM RTL bitvector cycle accurate synthesis
void Master::response_thread(){ OCPTL2Response resp; while (true) { wait(ocp->ResponseStartEvent); ocp->getOCPResponse(resp); ocp->acceptResponse(10); } class OCPTL2Response{ SRespType SResp; int DataLength; int SThreadID; int prio; …} SystemC based TL2 OCP Channel OCP Channel OCP Master Request Burst Response Burst
OCP Channel Performance Monitor • Motivation • Current OCP monitor targets verification • simulation slowed down by clocked monitor • Design Goals • Support Performance Analysis of TLM models • Simulation efficiency • SystemC conformable implementation • Object Oriented Modularity • SCV compliant • enable hierarchical transaction recording
OCP Transaction Timing thread(){ ocp->sendRequest(req); wait(...) ocp->getResponse(resp); wait(...) ocp->acceptResponse(); } thread(){ ocp->getRequest(req); wait(...) ocp->acceptRequest(); wait(...) ocp->sendResponse(); } OCP Channel OCP Master OCP Slave Request t
OCP Transaction Timing thread(){ ocp->sendRequest(req); wait(...) ocp->getResponse(resp); wait(...) ocp->acceptResponse(); } thread(){ ocp->getRequest(req); wait(...) ocp->acceptRequest(); wait(...) ocp->sendResponse(); } OCP Channel OCP Master OCP Slave Request Response t
SCV based OCP Transaction Recording thread(){ ocp->sendRequest(req); wait(...) ocp->getResponse(resp); wait(...) ocp->acceptResponse(); } thread(){ ocp->getRequest(req); wait(...) ocp->sendResponse(); wait(...) ocp->acceptRequest(); } OCP Channel performance monitor OCP Master OCP Slave SCV transaction recording API transaction database SCV implementation
Channel Monitor - Basic Master_Port Slave_Port OCP I1 ms1 sl1
Channel Monitor – OCP Bursts OCP I1 ms1 sl1
Channel Monitor – OCP Threads OCP I1 ms1 sl1
Channel Monitor – Threads and Bursts OCP I1 ms1 sl1
req req resp resp Initiator 2 OI2 Bus OT2 Target 2 OI2 Bus OT2 Hierarchical Transaction Recording OCP I1 OCP T1 Initiator 1 Target 1 Bus OCP I2 OCP T2 Initiator 2 Target 2
System Monitor - Bridge Slave Master OCP 1 OCP 2 ms1 br1 sl1
System Monitor – Bus, 1 Master OCP 2 sl0 OCP 1 ms bus OCP 3 sl1
System Monitor – Bus, 2 Masters OCP 3 OCP 1 ms0 sl0 bus OCP 4 OCP 2 ms1 sl1
Outlook: OCP TLM for Architectural Modeling • methodology document • timing annotation, performance modeling • coding guidelines and examples • configurable traffic generator, slaves, multi-master bus, systems • demonstrate OSCI TLM standard compliance • implement TL2 channel on top of TLM standard • relation to other TLM use-models and coding styles • Programmers View • Verification View
ocp_tl2_channel:public sc_module ocp_tl2_channel_monitor: public sc_module ocp_tl2_channel_monitor_reg_if: virtual public sc_interface ocp_tl2_channel_monitor_if channel monitor retrieves instance of system monitor from registry ocp_tl2_system_monitor_registry sc_port<ocp_tl2_channel_monitor_reg_if> // only 1 instance in whole system ocp_tl2_channel_monitor_scv ocp_tl2_system_monitor_if // only 1 instance in whole system ocp_tl2_system_monitor_scv // only 1 instance in whole system C++ Software Architecture of OCP TL2 Monitor SystemC