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Scoreboarding

Scoreboarding. Vincent H. Berk October 5, 2005 Reading for today: A7, A9-A11, article: Yeager Reading for Friday: A.8, article: Smith&Pleszkun. Scoreboard Implications (hardware ILP). Out-of-order completion  WAR, WAW hazards? Solutions for WAR

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Scoreboarding

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  1. ENGS 116 Lecture 7 Scoreboarding Vincent H. Berk October 5, 2005 Reading for today: A7, A9-A11, article: Yeager Reading for Friday: A.8, article: Smith&Pleszkun

  2. ENGS 116 Lecture 7 Scoreboard Implications (hardware ILP) • Out-of-order completion  WAR, WAW hazards? • Solutions for WAR • Queue both the operation and copies of its operands • Read registers only during Read Operands stage • For WAW, must detect hazard: stall until other write completes • Need to have multiple instructions in execution phase  multiple execution units or pipelined execution units • Scoreboard keeps track of dependences, state, and operations • Scoreboard replaces ID, EX, WB with 4 main stages • The EX stage can be (sub-)pipelined

  3.     Integer unit FP add FP divide FP mult FP mult Scoreboard ENGS 116 Lecture 7 Figure A.51 The basic structure of a DLX processor with a scoreboard Registers Data buses Control/status Control/status

  4. ENGS 116 Lecture 7 Four Stages of Scoreboard Control: ISSUE 1. Issue: decode instructions & check for structural hazards (ID1) If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared. Algorithm: • Assure In-Order issue • Multiple issues per cycle are allowed • Check if Destination Register is already reserved for writing (WAW) • Check if Read-Operand stage of Functional Unit is free (Structural)

  5. ENGS 116 Lecture 7 Four Stages of Scoreboard Control:READ-OPERANDS • Read operands: wait until no data hazards, then read operands (ID2) – First Functional Pipeline Stage A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order. Algorithm: • Wait for operands to become available, Register Result Status (RAW) • Operand Caching is allowed • Forwarding from another WB stage is allowed

  6. ENGS 116 Lecture 7 Four Stages of Scoreboard Control 3. Execution: operate on operands (EX) • The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. This stage can be (sub-)pipelined. 4. Write result: finish execution (WB) • Once the scoreboard is aware that the functional unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, it stalls the instruction. Algorithm: • Delay write until all Rj and Rk fields for this register are marked as either cached or read. • If caching of operands is done: forward answer right away. • If not, wait until all operands are read before writing. • Forward answers to units waiting for this write for their operand.

  7. ENGS 116 Lecture 7 Three Parts of the Scoreboard 1. Instruction status: Indicates which of 4 steps the instruction is in. 2. Functional unit status: Indicates the state of the functional unit (FU). 9 fields for each functional unit • Busy – Indicates whether the unit is busy or not • Op – Operation to perform in the unit (e.g., + or -) • Fi – Destination register • Fj, Fk – Source-register numbers • Qj, Qk – Functional units producing source registers Fj, Fk • Rj, Rk – Flags indicating when Fj, Fk are available and not yet read. (Alternatively: read and cached) 3. Register result status: Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register.

  8. ENGS 116 Lecture 7 Instruction status Functional unit status Register result status FIGURE A.52 Components of the scoreboard

  9. ENGS 116 Lecture 7 Scoreboard Example Cycle 1 R2 has not been read/cached until cycle 2!!!

  10. ENGS 116 Lecture 7 Scoreboard Example Cycle 2 Issue 2nd LD or MULT?

  11. ENGS 116 Lecture 7 Scoreboard Example Cycle 4 Yes

  12. ENGS 116 Lecture 7 Scoreboard Example Cycle 5 SUPERSCALAR: Issue MULTD?

  13. ENGS 116 Lecture 7 Scoreboard Example Cycle 6

  14. ENGS 116 Lecture 7 Scoreboard Example Cycle 7 Read multiply operands? DIVD could have been issued on this cycle.

  15. ENGS 116 Lecture 7 Scoreboard Example Cycle 8a

  16. ENGS 116 Lecture 7 Scoreboard Example Cycle 8b

  17. ENGS 116 Lecture 7 Scoreboard Example Cycle 9 Issue ADDD?

  18. ENGS 116 Lecture 7 Scoreboard Example Cycle 11

  19. ENGS 116 Lecture 7 Scoreboard Example Cycle 12

  20. ENGS 116 Lecture 7 Scoreboard Example Cycle 13

  21. ENGS 116 Lecture 7 Pipelining Functional Units • Would add multiple ‘virtual’ FUs to scoreboard • Lower hardware cost than multiple actual units • Inherently avoids WAW • Bubbles are inserted at Issue and Read-Op • Works best with more actual registers • Consider the example from the book: • Mult 1&2 are a two stage pipeline

  22. ENGS 116 Lecture 7 Superscalar: Multiple Issues per cycle • Very tedious • ENSURE in order issue to avoid hazards • Issuing hardware has to have ‘look-ahead’ hardware • Works best with multiple internally pipelined Fus • Consider: DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F8, F8, F14

  23. ENGS 116 Lecture 7 Exceptions • Imprecise due to out-of-order execution • Improved by keeping track of recently executed instructions: • Instructions are ‘retired’ in order • Synchronous exceptions raised at retirement • Operating system responsible for recovery • Non-fatal Asynchronous exceptions let pipeline and scoreboard run empty before context switch. • Trap/INT instructions (system calls) require context switch. • On context switch, pipeline and scoreboard is run empty.

  24. ENGS 116 Lecture 7 Scoreboarding Summary • Limitations of CDC 6600 scoreboard • No forwarding hardware • Limited to instructions in basic block (small window) • Small number of functional units (structural hazards), especially integer/load/store units • Do not issue if structural or WAW hazards • Wait for WAR hazards • Imprecise exceptions • Key idea: Allow instructions behind stall to proceed • Decode  issue instructions and read operands • Enables out-of-order execution  out-of-order completion

  25. ENGS 116 Lecture 7 Scoreboarding Summary • Modern Day Improvements: • All operands are cached as soon as available • Forwarding • Pipelining Functional Units • Microcoding, eg. IA32 (widens execution window) • More precise exceptions • In order retirement • Works best with tons of actual registers • Tomasulo approach: • Reservation stations vs. Forwarding and Caching • Temporary Registers work as many virtual registers

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