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October 8 th , 2008 Majd F. Sakr msakr@qatar.cmu qatar.cmu/~msakr/15447-f08/

CS-447– Computer Architecture Lecture 14 Pipelining (2). October 8 th , 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/. 6 PM. Midnight. 7. 8. 9. 11. 10. Time. 30. 30. 30. 30. 30. 30. 30. 30. 30. 30. 30. 30. T a s k O r d e r. A. B. C.

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October 8 th , 2008 Majd F. Sakr msakr@qatar.cmu qatar.cmu/~msakr/15447-f08/

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  1. CS-447– Computer Architecture Lecture 14Pipelining (2) October 8th, 2008 Majd F. Sakrmsakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/

  2. 6 PM Midnight 7 8 9 11 10 Time 30 30 30 30 30 30 30 30 30 30 30 30 T a s k O r d e r A B C D Sequential Laundry washing = drying = folding = 30 minutes

  3. 30 30 30 30 30 30 30 30 30 30 30 30 A B C D Sequential Laundry 6 PM Midnight 7 8 9 11 10 Time T a s k O r d e r

  4. 6 PM Midnight 7 8 9 11 10 Time 30 30 30 30 30 30 30 30 30 30 30 30 T a s k O r d e r A A B B C C D D Sequential Laundry 6 PM Midnight 7 8 9 11 10 Time 30 30 30 30 30 30 T a s k O r d e r • Ideal Pipelining: • 3-loads in parallel • No additional resources • Throughput increased by 3 • Latency per load is the same

  5. A B C D Sequential Laundry – a real example 6 PM Midnight 7 8 9 11 10 Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k O r d e r washing = 30; drying = 40; folding = 20 minutes

  6. 30 40 40 40 40 20 A B C D Pipelined Laundry - Start work ASAP 6 PM Midnight 7 8 9 11 10 • Drying, the slowest stage, dominates! Time T a s k O r d e r

  7. 30 40 40 40 40 20 A B C D Pipelining Lessons • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Pipeline rate limited by slowest pipeline stage • Multiple tasks operating simultaneously • Potential speedup = Number pipe stages • Unbalanced lengths of pipe stages reduces speedup • Time to “fill” pipeline and time to “drain” it reduces speedup 6 PM 7 8 9 Time T a s k O r d e r

  8. Pipelining • Doesn’t improve latency! • Execute billions of instructions, so throughputis what matters!

  9. Ideal Pipelining • When the pipeline is full, after every stage one task is completed.

  10. IFetch IFetch IFetch Dec Dec Dec Exec Exec Exec Mem Mem Mem WB WB WB Pipelined Processor • Start the next instruction while still working on the current one • improves throughputorbandwidth - total amount of work done in a given time (average instructions per second or per clock) • instruction latency is not reduced (time from the start of an instruction to its completion) • pipeline clock cycle (pipeline stage time) is limited by the slowest stage • for some instructions, some stages are wasted cycles Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 lw sw R-type

  11. IFetch Dec Exec Mem WB IFetch Dec Exec Mem IFetch “wasted” cycles IFetch Dec Exec Mem WB IFetch Dec Exec Mem WB IFetch Dec Exec Mem WB Single Cycle, Multiple Cycle, vs. Pipeline Single Cycle Implementation: Cycle 1 Cycle 2 Clk Load Store Waste Multiple Cycle Implementation: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw sw R-type Pipeline Implementation: lw sw R-type

  12. IFetch Dec Exec Mem WB IFetch Dec Exec Mem IFetch IFetch Dec Exec Mem WB IFetch Dec Exec Mem WB IFetch Dec Exec Mem WB Multiple Cycle v. Pipeline, Bandwidth v. Latency Multiple Cycle Implementation: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw sw R-type Pipeline Implementation: lw sw R-type • Latency per lw = 5 clock cycles for both • Bandwidth of lw is 1 per clock clock (IPC) for pipeline vs. 1/5 IPC for multicycle • Pipelining improves instruction bandwidth, not instruction latency

  13. Pipeline Datapath Modifications • What do we need to add/modify in our MIPS datapath? • registers between pipeline stages to isolate them IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack 1 0 Add Add 4 Shift left 2 Read Addr 1 Instruction Memory Data Memory Register File Read Data 1 Read Addr 2 IFetch/Dec Read Address PC Read Data Dec/Exec Address 1 Exec/Mem Write Addr ALU Read Data 2 Mem/WB 0 Write Data 0 Write Data 1 Sign Extend 16 32 System Clock

  14. DM Reg Reg IM ALU Graphically Representing the Pipeline Can help with answering questions like: • how many cycles does it take to execute this code? • what is the ALU doing during cycle 4?

  15. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Time to fill the pipeline Why Pipeline? For Throughput! Time (clock cycles) Inst 0 Once the pipeline is full, one instruction is completed every cycle I n s t r. O r d e r Inst 1 Inst 2 Inst 3 Inst 4

  16. 1 2 3 4 5 Load Ifetch Reg/Dec Exec Mem Wr 1 2 3 4 R-type Ifetch Reg/Dec Exec Wr Important Observation • Each functional unit can only be used once per instruction (since 4 other instructions executing) • If each functional unit used at different stages then leads to hazards: • Load uses Register File’s Write Port during its 5th stage • R-type uses Register File’s Write Port during its 4th stage • 2 ways to solve this pipeline hazard.

  17. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Solution 1: Insert “Bubble” into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 • Insert a “bubble” into the pipeline to prevent 2 writes at the same cycle • The control logic can be complex. • Lose instruction fetch and issue opportunity. • No instruction is started in Cycle 6! Clock Load R-type Pipeline R-type R-type Bubble

  18. Ifetch Reg/Dec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Solution 2: Delay R-type’s Write by One Cycle • Delay R-type’s register write by one cycle: • Now R-type instructions also use Reg File’s write port at Stage 5 • Mem stage is a NOP stage: nothing is being done. 4 1 2 3 5 R-type Exec Mem Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type R-type

  19. Can Pipelining Get Us Into Trouble? • Yes:Pipeline Hazards • structural hazards: attempt to use the same resource by two different instructions at the same time • data hazards: attempt to use data before it is ready • instruction source operands are produced by a prior instruction still in the pipeline • load instruction followed immediately by an ALU instruction that uses the load operand as a source value • control hazards: attempt to make a decision before condition has been evaluated • branch instructions • Can always resolve hazards by waiting • pipeline control must detect the hazard • take action (or delay action) to resolve hazards

  20. Structural Hazard • Attempt to use same hardware for two different things at the same time. • Solution 1: Wait • Must detect hazard • Must have mechanism to stall • Solution 2: Throw more hardware at the problem

  21. Reading data from memory Mem Mem Mem Mem Mem Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg Mem Mem Mem Mem Mem ALU ALU ALU ALU ALU Reading instruction from memory A Single Memory Would Be a Structural Hazard Time (clock cycles) lw I n s t r. O r d e r Inst 1 Inst 2 Inst 3 Inst 4

  22. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU How About Register File Access? Time (clock cycles) Can fix register file access hazard by doing reads in the second half of the cycle and writes in the first half. add r1, I n s t r. O r d e r Inst 1 Inst 2 add r2,r1, Inst 4 Potential read before write data hazard

  23. Three Generic Data Hazards • Read After Write (RAW)InstrJ tries to read operand before InstrI writes it • Caused by a “Data Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. I: add r1,r2,r3 J: sub r4,r1,r3

  24. I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards • Write After Read (WAR)InstrJ writes operand before InstrI reads it • Called an “anti-dependence” by compiler writers.This results from reuse of the name “r1”. • Can’t happen in MIPS 5 stage pipeline because: • All instructions take 5 stages, and • Reads are always in stage 2, and • Writes are always in stage 5

  25. I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards Write After Write (WAW)InstrJ writes operand before InstrI writes it. • Called an “output dependence” by compiler writersThis also results from the reuse of name “r1”. • Can’t happen in MIPS 5 stage pipeline because: • All instructions take 5 stages, and • Writes are always in stage 5

  26. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Register Usage Can Cause Data Hazards • Dependencies backward in time cause hazards add r1,r2,r3 I n s t r. O r d e r sub r4,r1,r5 and r6,r1,r7 or r8, r1, r9 xor r4,r1,r5 Which are read before write data hazards?

  27. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Loads Can Cause Data Hazards • Dependencies backward in time cause hazards lw r1,100(r2) I n s t r. O r d e r sub r4,r1,r5 and r6,r1,r7 or r8, r1, r9 xor r4,r1,r5 Load-use data hazard

  28. DM DM DM Reg Reg Reg Reg Reg Reg stall IM IM IM ALU ALU ALU stall sub r4,r1,r5 and r6,r1,r7 One Way to “Fix” a Data Hazard Can fix data hazard by waiting – stall – but affects throughput add r1,r2,r3 I n s t r. O r d e r

  29. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Another Way to “Fix” a Data Hazard Can fix data hazard by forwarding results as soon as they are available to where they are needed. add r1,r2,r3 I n s t r. O r d e r sub r4,r1,r5 and r6,r1,r7 or r8, r1, r9 xor r4,r1,r5

  30. DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Forwarding with Load-use Data Hazards • Will still need one stall cycle even with forwarding lw r1,100(r2) I n s t r. O r d e r sub r4,r1,r5 and r6,r1,r7 or r8, r1, r9 xor r4,r1,r5

  31. Control Hazards • Caused by delay between the fetching of instructions and decisions about changes in control flow • Branches • Jumps

  32. DM DM DM Reg Reg Reg Reg Reg Reg IM IM IM IM ALU ALU ALU ALU beq DM Reg Reg Branch Instructions Cause Control Hazards • Dependencies backward in time cause hazards I n s t r. O r d e r lw Inst 3 Inst 4

  33. DM DM Reg Reg Reg Reg IM IM IM ALU ALU ALU stall stall stall lw DM Reg Inst 3 One Way to “Fix” a Control Hazard beq Can fix branch hazard by waiting – stall – but affects throughput I n s t r. O r d e r

  34. 1 ID/EX 0 EX/MEM IF/ID Control Add MEM/WB Add 4 Shift left 2 Read Addr 1 Instruction Memory Data Memory Register File Read Data 1 Read Addr 2 Read Address PC Read Data Address 1 Write Addr ALU Read Data 2 0 Write Data 0 Write Data 1 Sign Extend 16 32 Pipeline Control Path Modifications • All control signals can be determined during Decode • and held in the state registers between pipeline stages

  35. Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1:

  36. Performance • Speed Up  Pipeline Depth; if ideal CPI is 1, then: • Time is measure of performance: latency or throughput • CPI Law: CPU time = Seconds = Instructions x Cycles x Seconds Program Program InstructionCycle

  37. DM Reg Reg IM IM ALU ALU DM2 DM1 Reg Reg Other Pipeline Structures Are Possible • What about (slow) multiply operation? • let it take two cycles MUL • What if the data memory access is twice as slow as the instruction memory? • make the clock twice as slow or … • let data memory access take two cycles (and keep the same clock rate)

  38. Reg EX DM Reg Reg IM IM ALU ALU Sample Pipeline Alternatives (for ARM ISA) • ARM7(3-stage pipeline) • StrongARM-1(5-stage pipeline) • XScale(7-stage pipeline) PC update IM access decode reg access ALU op DM access shift/rotate commit result (write back) Reg DM2 IM1 DM1 IM2 Reg SHFT PC update BTB access start IM access decode reg 1 access DM write reg write ALU op start DM access exception shift/rotate reg 2 access IM access

  39. Summary • All modern day processors use pipelining • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Multiple tasks operating simultaneously using different resources • Potential speedup = Number of pipe stages • Pipeline rate limited by slowest pipeline stage • Unbalanced lengths of pipe stages reduces speedup • Time to “fill” pipeline and time to “drain” it reduces speedup • Must detect and resolve hazards • Stalling negatively affects throughput

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