Pertemuan 22 IA-64 Architecture

1. Pertemuan 22IA-64 Architecture Matakuliah : H0344/Organisasi dan Arsitektur Komputer Tahun : 2005 Versi : 1/1

2. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Menjelaskan IA-64 Architecture secara garis besar

3. Outline Materi • Motivation • General Organization • Prediction, Speculative, and Software Pipelining • IA-64 Instruction Set Architecture • Itanium Organization

4. Motivation The basic concepts underlying IA-64 are as follows: • Instruction level parallelism that is explicit in the machine instructions rather that being determined at run time by the processor. • Long or very long instruction words (LIW/VLIW). • Branch predicating (not the same thing as branch prediction). • Speculative loading.

5. Motivation Traditional superscalar versus IA-64 architecture

6. General organization The key features of an IA-64 are as follows: • Large number of registers • Multiple execution units Four types of execution unit are defined in the IA-64 architecture: • I-unit • M-units • B-units • F-unit

7. General organization General organization for IA-64 architecture

8. General organization Relationship between instruction type and execution unit type

9. Predication, speculation, and software pipelining IA-64 instruction format

10. Predication, speculation, and software pipelining Assembly language format [qp] mnemonic[.comp] dest=srcs Example ld8 r1 = [r5] ;; // first groupadd r3 = r1, r4 // second group ld8 r1 = [r5] // first groupsub r6 = r8, r9 ;; // first groupadd r3 = r1, r4 // second groupst8 [r6] = r12 // second group

11. Predication, speculation, and software pipelining IA-64 Predication and speculative loading

12. Predication, speculation, and software pipelining Predicated execution

13. Predication, speculation, and software pipelining Predicated execution

14. Predication, speculation, and software pipelining Control speculation

15. Predication, speculation, and software pipelining Control speculation if ((b[j] == true) && (a[I + j] == true) && (c[I – j] == true)) Assembly code (1) mov r2, &b[j] ; transfer contents of location ; b[j] to register r2(2) cmp r2, 1(3) jne L2(4) mov r4, &a[i + j](5) cmp r4, 1(6) jne L2(7) mov r6, &c[i – j](8) cmp r6, 1(9) jne L2(10)L1: <code for the path>(11)L2: <code for else path>

16. Predication, speculation, and software pipelining Code with speculation and prediction: (1) mov r1 = &b[j] // transfer contents of location // b[j] to register r1(2) mov r3 = &a[i + j](3) mov r5 = &c[i – j + 7](4) ld8 r2 = [r1] // load indirect via r1(5) ld8.s r4 = [r3](6) ld8.s r6 = [r5](7) cmp.eq p1, p2 = 1, r2(8) (p2) br L2(9) chk.s r4, recovery_a // fixup for loading a(10) cmp.eq p3, p4 = 1, r4(11) (p4) br L2(12) chk.a r6, recovery_b // fixup for loading b(13) cmp.eq p5, p6 = 1, r5(14) (p6) br L2(15)L1: <code for the path>(16)L2: <code for else path>

17. Predication, speculation, and software pipelining Revised code with speculation and predication: (1) mov r1 = &b[j] (2) mov r3 = &a[i + j](3) mov r5 = &c[i – j + 7](4) ld8 r2 = [r1] (5) ld8.s r4 = [r3](6) ld8.s r6 = [r5](7) cmp.eq p1, p2 = 1, r2(8) (p1) chk.s r4, recovery_a(9) (p1) cmp.eq p3, p4 = 1, r4(10) (p3) chk.a r6, recovery_b (11) (p3) cmp.eq p5, p4 = 1, r5(12) (p6) br L2(13)L1: <code for the path>(14)L2: <code for else path>

18. Predication, speculation, and software pipelining Data speculation ld8.a r6 = [r8] ;; add r5 = r6, r7 ;; st8 [r4] = r12 chk.a r6, recoverback: st8 [r18] = r5 st8 [r4] = r12 ld8 r6 = [r8] ;; add r5 = r6, r7 ;; st8 [r18] = r5 ld8.a r6 = [r8] ;; st8 [r4] = r12 ld8.c r6 = [r8]add r5 = r6, r7 ;; st8 [r18] = r5 recover: ld8 r6 = [r8] ;; add r5 = r6, r7 ;; br back

19. Predication, speculation, and software pipelining Software pipelining ld4 r32 = [r5], 4 ;;ld4 r33 = [r5], 4 ;;ld4 r34 = [r5], 4 add r36 = r32, r9 ;;ld4 r35 = [r5], 4add r37 = r33, r9st4 [r6] = r36, 4 ;;ld4 r36 = [r5], 4add r38 = r34, r9st4 [r6] = r37, 4 ;;add r39 = r35, r9st4 [r6] = r38, 4 ;;add r40 = r36, r9st4 [r6] = r39, 4 ;;st4 [r6] = r40, 4 ;; y[i] = x[i] + c L1: ld4 r4 = [r5], 4 ;; add r7 = r4, r9 ;; st4 [r6] = r7, 4 br.cloop L1 ;;

20. Predication, speculation, and software pipelining Software pipelining The key features that support software pipelining are as follows: • Automatic register renaming • Predication • Special loop terminating instructions

21. Predication, speculation, and software pipelining Software pipelining mov lc = 199 mov ec = 4 mov pr.rot = 1<<16 ;; L1: (p16) ld4 r32 = [r5], 4 (p17) --- (p18) add r35 = r34, r9 (p19) st4 [r6] = r36, 4 br.ctop L1 ;;

22. IA-64 instruction set architecture The register set of IA-64 • General registers • Floating point registers • Predicate registers • Branch registers • Instruction pointer • Current frame marker • User mask • Performance monitor data registers • Processor identifiers • Application registers

23. IA-64 instruction set architecture IA-64 application register set

24. IA-64 instruction set architecture IA-64 application registers

25. IA-64 instruction set architecture Register stack behavior on procedure call and return

26. General organization Itanium organization