Intel IA-64

1. Intel IA-64 Architecture Chehun Kim Glenn Ramos

2. Contents *Pipelining - Stages of pipelining *Microprogramming *Interconnection Structures

3. Pipelining Pipelining - A means of introducing parallelism in to the essentially sequential nature of a machine-instruction program. IA 64 uses following methods for branches Prefetching with predication Prefetching with rotating registers Architectural support for software pipelining Modulo scheduling

4. IA-64 Instruction Pipeline - The Intel IA-64 Architecture’s pipeline is divided into 10 stages. - This design was developed for a single cycle ALU (4 ALU’s globally bypassed) and for low latency from data cache.

5. IA-64 Pipeline WL.D – Word-Line Decode REG – Register Read EXE – Execute DET – Exception Detect WRB – Write-Back IPG – Instruction Pointer Generation FET – Fetch ROT- Rotate EXP – Expand REN – Rename

6. IA-64 Pipeline The IA-64 instruction pipeline’s 10 stages are grouped into 4 phases. - Front End - Instruction Delivery - Operand Delivery - Execution

7. Front End - Front-end consists of stages IPG, FET and ROT. - This phase is responsible for fetching up to 32 bytes into a pre-fetch buffer.

8. Instruction Delivery - This phase is composed of EXP and REN stages. - Dispersal of up to 6 instructions to 9 functional units occurs. - Implementation of registers for use in rotation and stacking occur.

9. Operand Delivery • This phase is composed of the WLD and REG stages. • Register files are accessed and • Accesses and updates a register scoreboard. This scoreboard is used to detect when individuals can proceed, so that a stall of 1 instruction in a bundle will not cause the entire bundle to stall. • Check for dependencies.

10. Execution - This phase consists of the EXE, DET and WRB stages. - In this phase, instructions are executed through the ALU and load/store units. - Exceptions are detected and NaTs are posted. - Instructions are retired and write-backs are performed.

11. Microprogramming • Intel IA-64 instruction set, EPIC, is a derived form of VLIW • EPIC, standing for explicitly parallel instruction computing • VLIW, standing for Very Long Instruction Word • VLIW can perform multiple operations per cycle using horizontal microinstructions • Remember that IA 64’s instruction word is 128 bits long and consists of 3 instructions

12. Interconnection Structure

13. Interconnection Structure • The processor uses a multidrop, shared system bus to provide four-way glueless multiprocessor system support. • The 64-bit system bus uses a source-synchronous data transfer to achieve 266-Mtransfers/ s, which enables a bandwidth of 2.1 Gbytes/s. • The combination of these features makes the Itanium processor system a scalable building block for large multiprocessor systems.

14. Interconnection sturcture • Source Synchronous Mode • In source synchronous mode, the clock to data phase relationship at the input pins is maintained at the clock and data ports of the IOE input register. This mode is recommended for source synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as the same I/O standard is used. • Multidrop Bus System • In multidrop bus systems when one device transmits, all others within range can receive

15. Summary • Pipeline • IA 64 has 10 stages • Microprogramming • EPIC • Interconnection Structure • IA 64 uses source-synchronous data transfer • The processor uses a multidrop, shared system bus

16. Sources http://www.eecs.harvard.edu/~dbrooks/cs146-spring2004/cs146-lecture12.pdf http://www.dig64.org/More_on_DIG64/microarch_ovw.pdf http://www.info.uni-karlsruhe.de/~rubino/ia64p/ieee/Optimizer_for_IA64.pdf http://www.lems.brown.edu/~iris/en291s9-04/lectures/Itanium_microarchitecture.pdf http://www.cs.clemson.edu/~mark/uprog.html