Designing Combinational Logic Circuits

1. Designing CombinationalLogic Circuits EE141

2. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In EE141

3. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit EE141

4. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks EE141

5. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high EE141

6. PMOS Transistors in Series/Parallel Connection EE141

7. CL CL CL CL Threshold Drops VDD VDD PUN S D VDD D S 0  VDD 0  VDD - VTn VGS PDN VDD 0 VDD |VTp| VGS D S VDD S D EE141

8. Complementary CMOS Logic Style EE141

9. Example Gate: NAND EE141

10. Example Gate: NOR EE141

11. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C EE141

12. Constructing a Complex Gate EE141

13. Cell Design • Standard Cells • General purpose logic • Can be synthesized • Same height, varying width • Datapath Cells • For regular, structured designs (arithmetic) • Includes some wiring in the cell • Fixed height and width EE141

14. Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND EE141

15. Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 M3 GND Mirrored Cell GND EE141

16. V DD Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” Out In 2 Rails ~10 GND Cell boundary EE141

17. V V DD DD Standard Cells With minimaldiffusionrouting With silicided diffusion Out In Out In GND GND EE141

18. V DD Standard Cells 2-input NAND gate A B Out GND EE141

19. V V DD DD Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter NAND2 Out Out In A B GND GND EE141

20. X PUN C i VDD X B A j PDN GND Stick Diagrams Logic Graph A j C B X = C • (A + B) C i A B A B C EE141

21. Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND EE141

22. Consistent Euler Path X C i VDD X B A j A B C GND EE141

23. OAI22 Logic Graph X PUN A C C D B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D EE141

24. Example: x = ab+cd EE141

25. Properties of Complementary CMOS Gates Snapshot • High noise margins : V and V are at and GND , respectively. V OH OL DD • No static power consumption : There never exists a direct path between V and DD V ( GND ) in steady-state mode . SS • Comparable rise and fall times: (under appropriate sizing conditions) EE141

26. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors EE141

27. Rp Rp Rp Rp Rp Rp A B A A B A Cint Rn CL CL CL Rn Rn Rn Rn B A A A B Cint Switch Delay Model Req A A NOR2 INV NAND2 EE141

28. Rp Rp B A Cint CL Rn A Input Pattern Effects on Delay • Delay is dependent on thepattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL Rn B EE141

29. Delay Dependence on Input Patterns A=B=10 A=1 0, B=1 A=1, B=10 Voltage [V] time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF EE141

30. Rp Rp 2 2 Rp Rp A B A B Rn Cint Cint CL CL Rn Rn Rn B A B A 1 1 Transistor Sizing 4 4 2 2 EE141

31. A D Transistor Sizing a Complex CMOS Gate B 8 6 4 3 C 8 6 4 6 OUT = D + A • (B + C) A 2 D 1 B 2 C 2 EE141

32. D C B A C3 C2 C1 CL Fan-In Considerations A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. B C D EE141

33. quadratic tpHL tp linear tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH fan-in EE141

34. tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out EE141

35. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO EE141

36. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic? EE141

37. Buffer example In Out CL 1 2 N For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path? EE141

38. Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W) g – logical effort (kRunitCunit) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1. EE141

39. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size EE141

40. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity EE141

41. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1 EE141

42. Logical Effort of Gates t pNAND g = p = d = t pINV Normalized delay (d) g = p = d = F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h) EE141

43. Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)f+2 t pINV Normalized delay (d) g = 1 p = 1 d = f+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (f) EE141

44. Logical Effort of Gates EE141

45. Add Branching Effort Branching effort: EE141

46. Multistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D = Sdi = Spi + Shi EE141

47. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay EE141

48. Logical Effort From Sutherland, Sproull EE141

49. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = G = H = h = a = b = EE141

50. Example: Optimize Path g = 1f = a g = 1f = 5/c g = 5/3f = c/b g = 5/3f = b/a Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59 EE141