Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems

1. Analysis and Synthesis ofCommunication-Intensive HeterogeneousReal-Time Systems Paul PopComputer and Information Science Dept.Linköpings universitet

2. Outline • Introduction • System-level design and modeling • Conditional process graph • The system platform • Time-driven vs. event-driven systems • Communication-intensive heterogeneous real-time systems • Time-driven systems • Scheduling and bus access optimization • Incremental mapping • Event-driven systems • Schedulability analysis and bus access optimization • Incremental mapping • Multi-Cluster Systems • Schedulability analysis and bus access optimization • Frame packing • Summary of contributions

3. Embedded Systems General purpose systems Embedded systems Microprocessor market shares Communication-intensive heterogeneous real-time systems

4. Embedded Systems Characteristics • Dedicated functionality (not general purpose computers) • Embedded into a host system • Complex architectures • Embedded systems design constraints • Correct functionality • Performance, timing constraints: real-time systems • Development cost, unit cost, size, power, flexibility, time-to-prototype, time-to-market, maintainability, correctness, safety, etc. • Difficult to design, analyze and implement • System-level design • Reuse and flexibility

5. System-Level Design Systemspecification System-leveldesign tasks In this thesis • Scheduling • Bus access optimization • Mapping Softwaremodel Hardwaremodel Softwaregeneration Hardwaresynthesis Softwareblocks Hardwareblocks Prototype Fabrication

6. P0 Subgraph corresponding to DCK P0 P1 P11 P1 P11 D D P2 P3 P2 P3 C C C P12 P13 P12 P6 K P6 K P4 P5 P14 P16 P14 P16 P8 P9 P15 P8 P9 P7 P17 P10 P17 P10 First processorSecond processorASIC P18 P18 Application Modeling

7. I/O Interface ... RAM ROM CPU ASIC ... Comm. controller Time Triggered Protocol (TTP) • Bus access scheme: time-division multiple-access (TDMA) • Schedule table located in each TTP controller: message descriptor list (MEDL) ... S0 S1 S2 SG S0 S1 S2 SG Slot TDMA Round Cycle of two rounds Cluster:one network Gateway Controller Area Network (CAN) • Priority bus, collision avoidance • Highest priority message wins the contention • Priorities encoded in the frame identifier

8. ... • On several clusters ... Distributed Safety-Critical Applications • Distributed applications • On a single cluster • Motivation • Reduce costs:use resources efficiently • Requirements:close to sensors/ actuators • Distributed applications are difficult to... • Analyze(e.g., guaranteeing timing constraints) • Design (e.g., efficient implementation)

9. Event-Driven vs. Time-Driven Systems • Event-driven systems • Activation of processes is done at the occurrence of significant events • Scheduling event-triggered activities • Fixed-priority preemptive scheduling • Response time analysis: calculate worst-case response times for each process • Schedulability test: response times smaller than the deadlines • Time-driven systems • Activation of processes is done at predefined points in time • Scheduling time-triggered activities • Static cyclic non-preemptive scheduling • Building a schedule table: static cyclic scheduling (e.g., list scheduling)

10. Outline • Introduction • System-level design and modeling • Conditional process graph • The system platform • Time-triggered vs. event-triggered • Communication-intensive heterogeneous real-time systems • Time-driven systems • Scheduling and bus access optimization • Incremental mapping • Event-driven systems • Schedulability analysis and bus access optimization • Incremental mapping • Multi-Cluster Systems • Schedulability analysis and bus access optimization • Frame packing • Summary of contributions

11. Output • Design implementation such that the application is schedulable and execution delay is minimized • Local schedule tables for each node • The sequence and size of the slots in a TDMA round • The MEDL (schedule table for messages) for each TTP controller Communicationinfrastructureparameters Scheduling and Bus Access Optimization • Input • Safety-critical application: set of conditional process graphs • The worst-case execution time of each process • The size of each messages • The system architecture and mapping are given • Time-driven systems • Single-cluster architecture • Time-triggered protocol • Non-preemptive static cyclic scheduling Time-driven systems

12. P1 P4 24 ms P3 P2 m3 m4 P1 S1 S0 m1 m2 Round 1 Round 2 Round 3 Round 4 Round 5 m1 m2 P1 P4 P3 P2 22 ms P2 P3 m3 m4 m1 S0 S1 m2 Round 1 Round 2 Round 3 Round 4 m3 m4 P4 P4 P1 20 ms P3 P2 m3 m4 m1 m2 S0 S1 Round 1 Round 2 Round 3 Scheduling and Optimization Example Time-driven systems

13. Scheduling and Optimization Strategy • List scheduling based algorithm • The scheduling algorithm has to take into consideration the TTP • Priority function for the list scheduling • Bus access optimization heuristics • Greedy heuristic, two variants • Greedy 1 tries all possible slot lengths • Greedy 2 uses feedback from the scheduling algorithm • Simulated Annealing • Produces near-optimal solutions in a very large time • Cannot be used inside a design space exploration loop • Used as the baseline for comparisons • Straightforward solution • Finds a schedulable application • Does not consider the optimization of the design Time-driven systems

14. Case study • Vehicle cruise controller • Used throughout the thesis Can We Improve the Schedules? Cost function: schedule length Average Percentage Deviation [%] Baseline:Simulated Annealing Number of processes Time-driven systems

15. P3 P2 P4 P1 “Classic” Mapping and Scheduling Example N1 N2 P1 N1 P4 P3 P2 N2 m3 m4 S1 S0 m1 m2 Bus Round 1 Round 2 Round 3 Round 4 Round 5 Time-driven systems

16. Incremental Design Process • Start from an already existing system with applications • In practice, very uncommon to start from scratch • Implement new functionality on this system (increment) • As few as possible modifications of the existing applications,to reduce design and testing time • Plan for the next increment:It should be easy to add functionality in the future Time-driven systems

17. Do not exist yetat Version N! Future applications Map and scheduleso that thefuture applicationswill have a chanceto fit Current applications Version N+1 N Minimal modificationsare performed tothe existingapplications Existing applications N-1 Incremental Mapping and Scheduling Time-driven systems

18. Incremental Mapping and Scheduling • Input • A set of existing applications modeled using process graphs • A current application to be mapped modeled using process graphs • Each process graph in an application has its own period and deadline • Each process has a potential set of nodes to be mapped on and a WCET • Characteristics of the future applications • The system architecture is given • Output • A mapping and scheduling of the current application, such that: • Requirement (a)constraints of the current application are satisfiedand minimal modifications are performed to the existing applications • Requirement (b)new future applications can be mapped on the resulted system Time-driven systems

19. Future application Current application Existing application The future application does not fit! (a) (b) Mapping and Scheduling Example Time-driven systems

20. Mapping and Scheduling Strategies • Design optimization problem • Design criteria reflect the degree to which a design supports an incremental design process • Design metrics quantify the degree to which the criteria are met • Heuristics to improve the design metrics • Ad-hoc approach • Little support for incremental design • Mapping Heuristic • Iteratively performs design transformations that improve the design Time-driven systems

21. Futureapplication Currentapplication Existingapplication Can We Support Incremental Design? Are the mapping strategies proposed facilitating the implementation of future applications? % of future applications mapped Number of processes in the current application existing applications: 400, future application: 80 Time-driven systems

22. Outline • Introduction • System-level design and modeling • Conditional process graph • The system platform • Time-triggered vs. event-triggered • Communication-intensive heterogeneous real-time systems • Time-driven systems • Scheduling and bus access optimization • Incremental mapping • Event-driven systems • Schedulability analysis and bus access optimization • Incremental mapping • Multi-Cluster Systems • Schedulability analysis and bus access optimization • Frame packing • Summary of contributions

23. Output • Worst-case response times (schedulability analysis) • Design implementation such that the application is schedulable and execution delay is minimized • The sequence and size of the slots in a TDMA round • The MEDL (schedule table for messages) for each TTP controller Communicationinfrastructureparameters Scheduling and Bus Access Optimization • Input • Safety-critical application: set of conditional process graphs • The worst-case execution time of each process • The size of each messages • The system architecture and mapping are given • Event-driven systems • Single cluster architecture • Time-triggered protocol • Fixed-priority preemptive scheduling Event-driven systems

24. P0 P1 27 P9 C P6 30 C P2 30 P3 25 P11 P10 25 32 24 P4 P7 22 P12 19 P5 G2 P8 G1 Conditional Process Graph Scheduling Deadline: 110 Event-driven systems

25. Scheduling of Messages using the TTP messages are dynamically produced by the processes frames are statically determined by the MEDL m1 m2 m3 m4 m5 S0 S1 Round 1 Round 2 Round 3 1. Single message per frame, allocated statically:Static Single Message Allocation 2. Several messages per frame, allocated statically:Static Multiple Message Allocation 3. Several messages per frame, allocated dynamically:Dynamic Message Allocation 4. Several messages per frame, split into packets, allocated dynamicallyDynamic Packets Allocation Event-driven systems

26. Single Message Dynamic Messages Dynamic Packets Multiple Messages Compartison… Cost function: degree of schedulability 16 12 Average Percentage Deviation [%] 8 4 0 80 160 240 320 400 Number of processes Event-driven systems

27. Process P2 misses its deadline! Swapping m1 with m2:all processes meet their deadlines. P1 P1 P2 P2 P3 P3 Putting m1 and m2 in the same slot:all processes meet their deadline,the communication delays are reduced. m1 m1 m2 m2 Optimizing Bus Access (Static Allocation) P1 P2 P3 m1 m2 Event-driven systems

28. Outline • Introduction • System-level design and modeling • Conditional process graph • The system platform • Time-triggered vs. event-triggered • Communication-intensive heterogeneous real-time systems • Time-driven systems • Scheduling and bus access optimization • Incremental mapping • Event-driven systems • Schedulability analysis and bus access optimization • Incremental mapping • Multi-Cluster Systems • Schedulability analysis and bus access optimization • Frame packing • Summary of contributions

29. Output • Worst case response times and bounds on the buffer sizes • Design implementation such that the application is schedulable and buffer sizes are minimized • Schedule table for TT processes • Priorities for ET processes • Schedule table for TT messages • Priorities for ET messages • TT bus configuration (TDMA slot sequence and sizes) System configurationparameters Communicationinfrastructureparameters Schedulability Analysis and Optimization • Input • An application modeled as a set of process graphs • Each process has an worst case execution time, a period, and a deadline • Each message has a known size • The system architecture and the mapping of the application are given • Multi-cluster systems • Two-cluster architecture • Time-triggered cluster • Time-triggered protocol • Non-preemptive static cyclic scheduling • Event-triggered cluster • Controller area network protocol • Fixed-priority preemptive scheduling ... ... Multi-cluster systems

30. Multi-Cluster Scheduling • Scheduling cannot be addressed separately for each type of cluster • The inter-cluster communication creates a circular dependency: • TTC static schedules (offsets)  ETC response times • ETC response times  TTC schedule table construction Application, Mapping,Architecture TT Bus Configuration Priorities Offsetearliest possible start time for an event-triggered activity ResponseTimes ResponseTimeAnalysis StaticScheduling Offsets Multi-Cluster Scheduling ScheduleTables Responsetimes Boundson thebuffer sizes Multi-cluster systems

31. ... ... P4 P4 P4 P1 P1 P1 N1 N1 N1 S1 m1 m2 m1 m1 m2 m2 m3 m3 m3 SG SG S1 SG S1 S1 SG S1 SG S1 SG SG SG TTP TTP TTP NG NG NG CAN CAN CAN O2 O2 O2 P2 P2 P2 N2 N2 N2 O3 O3 O3 Deadlinemet Deadlinemet Deadlinemissed! P3 P3 P3 Transformation: P2 is the high priority process on N2 Transformation: S1 is the first slot, m1 and m2 are sent sooner Optimization Example Multi-cluster systems

32. Optimization Strategies • OptimizeSchedule • Synthesizes the communication and assigns priorities to obtain a schedulable application • Based on a greedy approach • Cost function: degree of schedulability • OptimizeBuffers • Synthesizes the communication and assigns priorities to reduce the total buffer size • Based on a hill-climbing heuristic • Cost function: total buffer size • Straightforward solution • Finds a schedulable application • Does not consider the optimization of the design Multi-cluster systems

33. OptimizeSchedule Can We Improve Schedulability? Cost function: degree of schedulability 120 StraightforwardsolutionDoes not perform optimizations 100 80 Average Percentage Deviation [%] 60 OptimizeSchedule? 40 20 0 Simulated AnnealingNear-optimal values for the degree of schedulability 80 160 240 320 400 Number of processes

34. OptimizeBuffers Can We Reduce Buffer Sizes? Cost function: total buffer size 10k OptimizeScheduleDoes not optimize thetotal buffer size 8k 6k OptimizeBuffers? Average total buffer size [k] 4k Simulated AnnealingNear-optimal values forthe total buffer size 2k 0 80 160 240 320 400 Number of processes Multi-cluster systems

35. Outline • Introduction • System-level design and modeling • Conditional process graph • The system platform • Time-triggered vs. event-triggered • Communication-intensive heterogeneous real-time systems • Time-driven systems • Scheduling and bus access optimization • Incremental mapping • Event-driven systems • Schedulability analysis and bus access optimization • Incremental mapping • Multi-Cluster Systems • Schedulability analysis and bus access optimization • Frame packing • Summary of contributions

36. Thesis Contributions • Time-driven systems • Static scheduling strategy • Optimization strategies for the synthesis of the bus access scheme • Mapping and scheduling within an incremental design process • Event-driven systems • Schedulability analysis • Optimization strategies for the synthesis of the bus access scheme • Mapping and scheduling within an incremental design process • Multi-cluster systems • Schedulability analysis for multi-cluster systems • Optimization heuristics for system synthesis:minimal buffer sizes needed to run a schedulable application • Frame-packing optimization heuristics