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This research investigates the impact of Quantum Error Correction (QEC) data involvement on the execution time of quantum circuits. The study explores the use of ancilla factories and the design of a practical Qalypso architecture to optimize ancilla generation and ensure faster circuit execution. The goal is to match the production bandwidth to the data needs and minimize inter-region movement. Ancilla bandwidth is traded off with execution speed, and layout investigation shows that ancilla generation dominates area.
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Running a Quantum Circuitat the Speed of Data Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz U.C. Berkeley QEC 2007
QEC Step X QEC Step QEC Step Parallel Latency Serial Latency The Impact of QEC Data Involvement in QEC Step H Zero Ancilla Prep Zero Ancilla Prep Zero Ancilla Prep time
Data Involvement hardware time The Speed of Data • Non-Transversal Logical Gate • Zhou et al., Phys. Rev. A, 62(5):52316 • Ideally, execution time determined solely by data Non-Transversal Ancilla Prepare
Limited BW Graph • 32-bit Quantum Carry-Lookahead Adder in Ion Traps • Varying rate at which encoded zero ancillae are provided for QEC • Conclusion: design architecture with “ancilla factories”
Idealized Qalypso Architecture • Dense data region • Data qubits only • Local communication • Shared Ancilla Factories • Distributed to data as needed • Fully multiplexed to all data • Output ports ( ): close to data • Input ports ( ): may be far from data, since recycled qubits have irrelevant state • Goals • Design ancilla factories • Answer Question: How much hardware is needed for ancilla generation to run at the speed of data?
Automated toolset to assist in architecture design Ion trap technology Local gates: two qubits in the same trap Basic block abstraction: to avoid unknown electrode details straight 3-way 4-way turn gate locations Our Quantum CAD Toolset Dr. Hensinger, University of Sussex 3-way intersection • Our basic layout blocks
Identical Circuits Steane, Multiple-Particle Interference and QEC Level 1 [[7,1,3]] QEC Circuits
Encoded Ancilla Verification Qubits In-place Prep In-place Prep In-place Prep In-place Prep Zero Ancilla Factory Design I • “In-place” ancilla preparation • Ancilla factory consists of many of these • Encoded ancilla prepared in many places • But we want input and output ports
Zero Ancilla Factory Design II • Pipelined ancilla preparation: break into stages • Match physical qubit bandwidth between stages for high utilization • Steady stream of encoded ancillae at output port Physical 0 Prep CNOTs Verif X/Z Correct Cat Prep Junk Physical Qubits Good Encoded Ancillae Crossbar Crossbar Crossbar CNOTs Physical 0 Prep X/Z Correct Cat Prep Verif Recycle cat state qubits and failures Recycle used correction qubits
Practical Qalypso Architecture • Multiple Data Regions • Each serviced by local ancilla factories • Communication network moves data between regions (not shown) • Data regions as large as possible to get benefits of minimizing inter-region movement and multiplexing ancilla factory output
Summary • Investigated removing ancilla generation from critical path • Operations on data qubits dictate performance • Tradeoff in ancilla bandwidth vs execution speed • Architectural approach: ancilla factories • Match production bandwidth to needs of data • Pipelining places output ports close to data • Qalypso architecture • Dense data regions with local communication • Ancilla factories segregated from data • Multiplexing between factories and data • Input and output ports • Layout investigation => ancilla generation dominates area
