Fundamentals of CMOS VLSI

1. Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56 Prepared By: Aswini N, Praphul M N Department: ECE Date: 10/11/2014 Engineered for Tomorrow Prepared by : MN PRAPHUL & ASWINI N Assistant professor ECE Department Date : 11/10/14

2. Engineered for Tomorrow syllabus • Unit-1 : Basic Cmos Technology. 3 hrs • Mos transistor theory. 4 hrs • Unit-2 : Circuit Design Process 4 hrs • Unit-3 : Cmos Logic Structures 6 hrs • Unit-4 : Basic circuit concepts 3 hrs • Scaling of MOS circuits 3 hrs • Unit-5 : CMOS Subsystem design 5 hrs • Clocking stratagies 2 hrs • Unit-6 : CMOS Subsystem design process 6 hrs • Unit-7 : Memory,registers and clock 6 hrs • Unit-8 Testability 7 hrs

3. Engineered for Tomorrow Hello friends!.. you are on a way to understand one of the most fascinating fields of modern times.Welcome to the world of VLSI.

4. Engineered for Tomorrow Unit 1 a.Basic MOS Technology b.MOS transistor theory

5. Engineered for Tomorrow Syllabus • Integrated Circuit’s era. • Enhancement and Depletion mode MOS transistors. • Nmos Fabrication • CMOS Fabrication. • Thermal aspects of Processing • BICMOS technology • Production of E-beam masks

6. Engineered for Tomorrow Integrated Circuit’s era • What is an IC?? • IC is abbreviated as Integrated circuit.IC consists of an electronic switching networks that are created on small area of a silicon wafer using a complex set of physical and chemical processes. • Transistors are used as switching components. • Transistor was first invented by William.B.ShockleyWalter Brattain and John Bardeenof Bell Labratories. • In 1961, first IC was introduced.

7. Engineered for Tomorrow Levels of transistors integrated

8. Engineered for Tomorrow Moore’s Law “The number of transistors embedded on the chip doubles after every one and a half years.” ---Gordon Moore, cofounder Intel Corporation Fig 1. Moore's graph

9. Engineered for Tomorrow Types of Field Effect Transistors (The Classification)

10. Engineered for Tomorrow Field-Effect Transistor (FET) • Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely popular since the late 1970s. • Compared to BJTs, MOS transistors: • Can be made smaller /higher integration scale • Easier to fabricate /lower manufacturing cost • Simpler circuitry for digital logic and memory • Inferior analog circuit performance (lower gain) • Most digital ICs use MOS technology

11. Gate Oxide Gate Polysilicon Field-Oxide Source Drain (SiO ) 2 n+ n+ p+ stopper p-substrate Bulk Contact Fig 2. CROSS-SECTION of NMOS Transistor Engineered for Tomorrow MOS Transistors

12. Engineered for Tomorrow MOS transistors Symbols

13. Gate | VGS | Source (of carriers) Drain (of carriers) Closed (on) (Gate = ‘1’) Open (off) (Gate = ‘0’) Ron | VGS | < | VT | | VGS | > | VT | Engineered for Tomorrow Switch Model of NMOS Transistor

14. Gate | VGS | Source (of carriers) Drain (of carriers) Closed (on) (Gate = ‘0’) Open (off) (Gate = ‘1’) Ron | VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| | Engineered for Tomorrow Switch Model of PMOS Transistor

15. Engineered for Tomorrow MOSFETs- Enhancement Type The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

16. Engineered for Tomorrow Physical Operation of Enhancement MOSFET • If S and D are grounded and a positive voltage is applied to G, the holes are repelled from the channel region downwards, leaving behind a carrier-depletion region. • Further increasing VG attracts minority carrier ( electrons) from the substrate into the channel region. • When sufficient amount of electrons accumulate near the surface of the substrate under the gate, an n region is created-called as the inversion layer.

17. Engineered for Tomorrow N-Channel enhancement mode

18. Engineered for Tomorrow p-channel enhancement mode Output characteristics Transfer characteristics

19. Engineered for Tomorrow Field-Effect Transistors (FETs) Depletion Type • The depletion type MOSFET has similar structure to that the enhancement type MOSFET but with one important difference • The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion-type MOSFET has an n-type silicone region connecting the source and drain (both +n) at the top of the type substrate. • The channel depth and hence its conductivity is controlled by vGS. Applying a positive vGS enhances the channel by attracting more electrons. The reverse when applying negative volt. The negative voltage is said to deplete the channel (depletion mode).

20. Engineered for Tomorrow p and n channel depletion mode characteristics

21. Engineered for Tomorrow MOS transistor action • Three distinct region • Cutoff region • Linear region • Saturation region.

22. gate source drain VGS<VT0 IDS=0 Engineered for Tomorrow Cutoff Region • Assume n-channel MOSFET and VSB=0 Cutoff Mode: 0≤VGS<VT0 • The channel region is depleted and no current can flow

23. gate source current drain VDS < VGS – VT0 IDS Engineered for Tomorrow Linear Region Linear (Active, Triode) Mode: VGS≥VT0, 0≤VDS≤VD(SAT) • Inversion has occurred; a channel has formed • For VDS>0, a current proportional to VDS flows from source to drain • Behaves like a voltage-controlled resistance

24. gate source current drain VDS = VGS – VT0 IDS Engineered for Tomorrow Pinch-Off Pinch-Off Point (Edge of Saturation) : VGS≥VT0, VDS=VD(SAT) • Channel just reaches the drain • Channel is reduced to zero inversion charge at the drain • Drifting of electrons through the depletion region between the channel and drain has begun

25. gate source drain VDS > VGS – VT0 IDS Engineered for Tomorrow Saturation Saturation Mode: VGS≥VT0, VDS≥VD(SAT) • Channel ends before reaching the drain • Electrons drift, usually reaching the drift velocity limit, across the depletion region to the drain • Drift due to high E-field produced by the potential VDS-VD(SAT) between the drain and the end of the channel

26. Engineered for Tomorrow Nmos/Cmos Fabrication Process • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well • Cover wafer with protective layer of SiO2 (oxide) • Remove layer where n-well should be built • Implant or diffuse n dopants into exposed wafer • Strip off SiO2

27. Engineered for Tomorrow Oxidation • Grow SiO2 on top of Si wafer • 900 – 1200 C with H2O or O2 in oxidation furnace

28. Engineered for Tomorrow Photoresist • Spin on photoresist • Photoresist is a light-sensitive organic polymer • Softens where exposed to light

29. Engineered for Tomorrow Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist

30. Engineered for Tomorrow Etch • Etch oxide with hydrofluoric acid (HF) • Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed

31. Engineered for Tomorrow Strip Photoresist • Strip off remaining photoresist • Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step

32. Engineered for Tomorrow Polysilicon • Deposit very thin layer of gate oxide • < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer • Place wafer in furnace with Silane gas (SiH4) • Forms many small crystals called polysilicon • Heavily doped to be good conductor

33. Engineered for Tomorrow Polysilicon Patterning • Use same lithography process to pattern polysilicon

34. Engineered for Tomorrow Self-Aligned Process • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact

35. Engineered for Tomorrow N-diffusion • Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

36. Engineered for Tomorrow N-diffusion cont… • Strip off oxide to complete patterning step

37. Engineered for Tomorrow P-Diffusion • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

38. Engineered for Tomorrow Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed

39. Engineered for Tomorrow Metallization • Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires

40. Engineered for Tomorrow Bicmos technology • BiCMOS' is an evolved semiconductor technology that integrates two formerly separate semiconductor technologies - those of the bipolar junction transistor and the CMOS transistor - in a single integrated circuit device. • Bipolar junction transistors offer high speed, high gain, and low output resistance, which are excellent properties for high-frequency analog amplifiers. • CMOS technology offers high input resistance and is excellent for constructing simple, low-power logic gates.

41. Engineered for Tomorrow Bicmos structure

42. Engineered for Tomorrow Bicmos technology process

43. Engineered for Tomorrow Threshold voltage (Vt) • The voltage at which an MOS device begins to conduct ("turn on") is a threshold voltage. The threshold voltage is a function of following parameters: • Gate conductor material • Gate insulator material • Gate insulator thickness • Impurity at the silicon-insulator interface • Voltage between the source and the substrate Vsb • Temperature

44. Engineered for Tomorrow Second Order Effects • Threshold voltage – Body effect • Subthreshold region • Channel length modulation • Mobility variation • Fowler_Nordheim Tunneling • Drain Punchthrough • Impact Ionization – Hot Electrons

45. Engineered for Tomorrow Sub-Threshold Behavior • For gate voltage less than the threshold – weak inversion • Diffusion is dominant current mechanism (not drift) • Sub-threshold current is exponential function of applied gate voltage • Sub-threshold current gets larger for smaller gates (L)

46. Engineered for Tomorrow Channel Length Modulation • With pinch-off the channel at the point y such that Vc(y)=VGS - VT0, The effective channel length is equal to L’ = L – ΔL ΔL is the length of channel segment over which QI=0. • Place L’ in the ID(SAT) equation: Fig2 .Illustrating channel length modulation

47. Engineered for Tomorrow Mobility • Drain current model assumed constant mobility in channel • Mobility of channel less than bulk – surface scattering • Mobility depends on gate voltage – carriers in inversion channel are attracted to gate – increased surface scattering – reduced mobility

48. Engineered for Tomorrow Drain punch through • Punch through in a MOSFET is an extreme case of channel length modulation where the depletion layers around the drain and source regions merge into a single depletion region. • The field underneath the gate then becomes strongly dependent on the drain-source voltage, as is the drain current. • Punch through causes a rapidly increasing current with increasing drain-source voltage. • This effect is undesirable as it increases the output conductance and limits the maximum operating voltage of the device

49. Engineered for Tomorrow CMOS(Complementary metal oxide semiconductor) NOT gate (inverter)

50. Engineered for Tomorrow CMOS Vout = 0 Vin = 1 Vout = 1 Vin = 0