SAT-based Methods: Logic Synthesis and Technology Mapping

1. SAT-based Methods: Logic Synthesis and Technology Mapping Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

2. Overview • Understanding a SAT solver • SAT-based ISOP computation • SAT-based technology mapping • Structural • Functional • SAT vs. other computation engines • Experimental results 2

3. Boolean Satisfiability • Given a formula representing Boolean function (x), satisfiability problem is to prove that (x)  0, or to find a counter-example x’ such that (x’)  1 • In many applications the formula is in CNF • CNF (Conjunctive Normal Form) is the product of sums, for example (x1, x2) =(x1 + x2)(!x1 + x2) • If CNF was canonical (like BDD), it would be trivial to solve the satisfiablity problem • But CNF is not canonical; CNF can be very redundant, so that a large formula is, in fact, equivalent to 0.

4. Example (Deriving CNF) CNF ab (a + b + c) (a + b + c’) (a’ + b + c’) (a + c + d) (a’ + c + d) (a’ + c + d’) (b’ + c’ + d’) (b’ + c’ + d) cd Cube: bcd’ Clause: b’ + c’ + d

5. Boolean Satisfiability Netlist Answer: “SAT” or “UNSAT” CNF SAT solver CNF generator CNF If SAT, a counter-example Design constraints If UNSAT, a proof (both counter-examples and proofs are very useful in practice) User cost functions Miter Output Typical application: Equivalence Checking Build circuit Miter = (Specification != Implementation) Convert Miter into CNF and run SAT solver - If UNSAT, equivalence checking succeeds - If SAT, use the counter-example to debug the design Impl Spec Inputs

6. Incremental SAT Solver Initial CNF SAT solver Round 1: Initial assumptions Additional CNF SAT solver Round 2: New assumptions Additional CNF SAT solver Round 3: New assumptions (assumptions are CNF clauses used only in the current round – they are handled differently from the rest) Typical application: Bounded Model Checking Load init and the first time frame until (SAT solver returns “UNSAT”) { add clauses for the next time frame } P P P … T1 T2 T3 Init

7. A Note on Counter-Examples • Counter-example (CEX) is an assignment of SAT variables that makes all CNF clauses satisfied • For this, we check whether ONSET(x) = 1 is true • CNF-based SAT solvers (in particular, MiniSAT), always return a complete assignment of variables (a minterm) • In practice incomplete assignments are often preferred • For this, we need to expand an assignment minterm by dropping (expanding) some of its literals, making it a cube • To expand an assignment, we use the off-set (similar to “expanding a cube against the off-set” in ESPRESSO) • We solve SAT instance: ONSET_minterm(x) & OFFSET(x) = 0 • A proof of unsatisfiability tells us what literals to expand

8. A Note on Proofs • Proof of unsatisfiability (POU), is a sequence of resolution steps, which derives empty clause (contradiction) from the original clauses • POU can be used to compute an UNSAT core (a subset of original clauses, which make the problem UNSAT) • Computing the full POU/core is often not necessary • A practical alternative computes an abstraction of the core in the form of a subset of assumptions needed for the problem to be UNSAT • This is achieved by a special API of the SAT solver (analyze_final) • This API is very fast because it simply performs conflict analysis one more time, on the top level • This API is very practical because it allows UNSAT runs to be as useful as SAT ones, without recording and traversing the complete POU

9. Irredundant SOP • ISOP is a Sum-of-Products (SOP) that is prime and irredundant • F = ab + cd is an ISOP; G= ab + a is not an ISOP • Logic synthesis derives circuit structure from functional description or improves given structure • Deriving ISOP and factoring it can be useful for this • Minato-Morreale ISOP computation is a BDD-based method widely used in practice • However, this method is not scalable; better methods are needed

10. Big Picture: Circuit Restructuring ISOP (as a ZDD) BDD traditional approach Improved circuit Boolean function as a circuit {ON-set, OFF-set} Factoring SAT-based ISOP CNF see next slide SAT-based Factoring This is joint work with Ana Petkovska and Paolo Ienne Lopez at EPFL future work

11. SAT-based ISOP Computation • Disclaimer! This is a simplified formulation of ISOP computation • assumes that only one phase of the SOP is computed (in practice, we compute both) • Algorithm • Input Boolean function as two (shared) circuits (ON-set and OFF-set) • Convert these to CNF • Initialize two SAT solvers (S1 for ON-set; S2 for OFF-set) • Iterate until S1 returns “UNSAT”: • Get one minterm of the ON-set (satisfiable assignment computed by S1) • Expand it into a prime against the OFF-set (proof computed by S2) • Add this prime to the SOP and block it in the ON-set (add clause to S1) • Post-process the SOP by removing redundant cubes (done using new solver S3) • Resulting ISOP is canonical because the same fixed variable order is used • to compute one satisfiable minterm • to expand minterm into a prime • to remove redundant primes if present • Canonicity (as in the case of BDDs) guarantees that the result is the same • for any structure of the circuit • for any CNF generation algorithm • for any SAT solver • for any operating system

12. SAT-based ISOP Computation one minterm SAT solver S2 (OFF-set) SAT solver S1 (ON-set) SAT solver S3 (sat assignment) redundant SOP irredundant SOP one prime cube CNF CNF blocking clause (analyze_final) Factoring Original circuit {ON-set, OFF-set} Factored form SOP generator Improved circuit

13. Achieving Canonicity of the SOP • Canonicity means that, for the given function, with the given variable order, we get the same SOP • independent of circuit structure, CNF, SAT solver, OS, etc • To this end, we have to canonicize the following steps • minterm selection (a non-trivial task) • cube expansion • redundant cube removal • Minterm is selected canonically by making sure that it is the lexicographically smallest SAT assignment under the variable order • Cube is expanded canonically by making sure that literals are removed in the given order • Redundant cubes are removed canonically by ordering them This is joint work with MathiasSoeken and Giovanni De Micheli at EPFL

14. LEXSAT Algorithm • Efficiently computes the lexicographically smallest assignment • The main building block of the canonical ISOP computation • if canonicity is not required, we can use any assignment • Pseudo-code assignment LEXSAT_rec( assigned vars A, unassigned vars U, cnf F ) { if ( F is UNSAT under assumptions in A ) return ‘none’; // no satisfiable assignment if ( U ==  ) return Const1; // constant 1 Boolean function v = next unassigned variable in U in the given order; result = LEXSAT_rec( A v=0, U / v, F ); if ( result != ‘none’ ) return !v & result; // found assignment with v == 0 return v & LEXSAT_rec( A v=1, U / v, F ); // found assignment with v == 1 } } assignment LEXSAT( ordered set of vars V, cnf F ) { return LEXSAT_rec( , V, F ); } LEXSAT is mentioned in Donald Knuth, Art of Computer Programming, Volume 4 (6A): http://www-cs-faculty.stanford.edu/~uno/fasc6a.ps.gz - Implementing LEXSAT by iterative SAT calls (Ex. 109, page 150) - LEXSAT as modification of another algorithm (Ex. 275, page 165)

15. SAT-based Structural Mapping • Input the original mapped circuit and the library • Iterate over small multi-output cones (10-20 gates each) in some order • Convert the cone into an AIG • Compute cuts and matches for each AIG node using the library • Describe the set of all structural gate covers of the cone as a CNF • Introduce one SAT variable for each node polarity and for each cut • If a node is used in the mapping, it implies that one of its cuts is used • If a cut is used, it implies that the root and the leaf nodes are used • The output nodes should be used in the mapping • Cardinality constraint limits the gate count • Solve incremental SAT • Incrementally reduce solution cardinality if needed • Timing constraints are handled as a SAT solver callback • If there is an improvement, replace original mapping of the cone by the new one • Output an improved circuit

16. CNF / Mapping Terminology • CNF is composed of variables, literals, and clauses • Each variable represents some aspect of the problem • Each literal is a variable in positive or negative polarity • Each clause is a disjunction of literals • CNF is a conjunction of clauses • Mapping is a set of gates completely covering the subject graph • Internal nodes of the subject graph can be • Used in the mapping (if mapping includes a gate rooted in this node) • Not used in the mapping (otherwise) • Gate cover represents a valid mapping if • Internal nodes driving the circuit outputs are used in the mapping • For each gate, its inputs are used in the mapping or are primary inputs

17. CNF for Structural Mapping • Disclaimer! This is a simplified formulation of standard-cell mapping • assumes one variable per node (rather than two variables for each polarity) • CNF variables • one variable (ni) for each node • ni is 1, iff node i is used in the mapping • one variable (cik) for each match (cut + gate) of the node • cik is 1, iff match k is used to map node I • CNF clauses • ni  k(cik) (If a node is used, one of its matches is used) • cik f (nf) (If a match is used, all cut fanins are used) • o (no)(The nodes driving the outputs are used in the mapping) • i ni ≤ Limit(The gate count does not exceed the known mapping)

18. Handling of Timing Constraints • Timing constraints can be simplified (discretized) and turned into CNF • However, this leads to an increase in CNF size and a slowdown in solving • A better way to handle such constraints, is to use a dedicated constraint propagation engine (in this case, a timer) • SAT solver and the timing engine interact similar to how SMT solver is built around a SAT solver and one or more domain solvers • SAT solver leads the constraint propagation and passes partial assignments to the domain solvers, which propagate them on the domain constraints and return learned clauses to SAT solver • In the context of a technology mapping, it means that SAT solver finds valid structural mappings, repeatedly evaluated by the timer • If the timer finds that the mapping meets the timing, a solution is found • Otherwise, the timer returns the critical path, which is interpreted as a blocking clause by the SAT solver • The SAT solver continues to explore the search space until it either • Finds a mapping that satisfying the timing • Returns UNSAT after exploring all valid mappings • Runs out of resources (runtime, memory, etc)

19. SAT-based Functional Mapping • Input the original mapped circuit and the library • Preprocess the library by combining gates into “super-gates” characterized by area, delay, and Boolean function (as a truth table) • Iterate over gates in some order • Compute a local window centered in this gate • Construct CNF of the Boolean relation relating the gate output and the outputs of other gates in the window • Use the SAT solver to perform recursive cofactoring of the Boolean relation, resulting in several alternative implementations of the gate • Express each implementation as a super-gate in the precomputated library • Evaluate each implementation in terms of area/delay and find the best one • If there is an improvement, replace original gate by the new one • Output an improved circuit

20. Window POs m = 3 k = 3 Window PIs Local Window of a Node • Definition • A window for a node in the network is the context, in which its functionality is considered • A window includes • k levels of the TFI • m levels of the TFO • all re-convergent paths captured in this scope

21. Constructing Boolean Relation of the Node and Candidate Divisors 1 Construction steps: • Collect candidate divisors diof node n • Divisors are not in the TFO of n • Their support is a subset of that of node n • Duplicate the window of node n • Use the same output variables • Add inverter for node n in one copy • Create comparator for the outputs • Set the comparator to 1 • This is the care set of node n • Convert all gates to CNF … d2 n n d1 How the relation is used: • Function n = F(d1, d2, …) belongs to the relation iff n can be implemented as a gate with function F in terms of divisors d1, d2, … • SAT solver is used to recursively cofactor the relation using different variable orders, resulting in several qualifying functions F X

22. SAT-based Relation Solving • Given Boolean relation in CNF, find contained Boolean function(s) • Pseudo-code function SolveBR_rec( ordered set of divisors D, assigned divisors A, cnf C ) { if ( F=1 is UNSAT under assumptions in A ) return 0; if ( F=0 is UNSAT under assumptions in A ) return 1; if ( F=di or F=!di for a divisor di in D under assumptions in A ) return di or !di; d = the topmost variable in D; return d ? SolveBR_rec( D/d, A d=1, C) : SolveBR_rec( D/d, A d=0, C); } functions SolveBR( number of functions N, set of divisors D, cnf C ) { result = ; for ( i = 0; i < N; i++ ) { find a new ordering of divisors in D; result = result SolveBR_rec( D, ,C ); } return result; }

23. SAT vs. Other Computation Engines • The presented computations can be implemented with any computation engine • SAT, BDDs, SOPs, truth tables, etc • The implementations differ greatly in terms of • Complexity • Resource usage • Quality of results • Scalability • Based on these metrics, SAT-based implementations are rated highly • Relatively easy to implement (using an off-the-shelf solver) • Relatively inexpensive (both memory and runtime requirements are reasonable) • Good quality of result (typically, there is no clear win against other method) • The most scalable among known engines (this is the main advantage!) • The main reason why SAT is more scalable than BDDs • BDDs require construction of a canonical form before they can be used • CNF construction is linear; therefore, SAT can start working on the problem right away • As a result, SAT has more chances to solve a hard instance of an NP-hard problem

24. Experimental Results • Experimenting only with SAT-based functional mapper • The results explore scalability of the mapper • Using 10 large combinational logic cones • A typical run abc 01> r ex02.aig; amap; ps; mfs3 -aev -I 4 -O 2; ps; time; echo ex02 : i/o =25237/18422 lat = 0 nd = 34817 edge = 110193 area =34817.00 delay =308.95 lev = 13 Library processing: Var = 6. Cell = 71. Fun = 38660. Obj = 38660. Ave = 1.00. Skip = 0. Rem = 0. Time = 0.07 sec Remapping parameters: TFO = 2. TFI = 4. FanMax = 10. MffcMin = 1. MffcMax = 3. DecMax = 1. 0-cost = no. Effort = yes. Sim = no. Node = 34817. Try = 34817. Change = 8764. Const0 = 0. Const1 = 0. Buf = 44. Inv = 7655. Gate = 1065. AndOr = 0. Effort = 962. MaxDiv = 111. MaxWin = 136. AveDiv = 8. AveWin = 11. Calls = 5442733. (Sat = 2698400. Unsat = 2744333.) Over = 0. T/O = 0. Lib = 0.07 sec ( 0.62 %) Win = 0.12 sec ( 1.06 %) Cnf = 0.10 sec ( 0.88 %) Sat = 10.98 sec ( 97.08 %) Sat = 8.19 sec ( 72.41 %) Unsat = 1.73 sec ( 15.30 %) Eval = 0.00 sec ( 0.00 %) Timing = 0.00 sec ( 0.00 %) Other = 0.04 sec ( 0.35 %) ALL = 11.31 sec (100.00 %) Cone sizes: 1=7699 2=5 3=164 4=34 5=861 6=1 Gate sizes: 1=7867 2=897 Reduction: Nodes 1210 out of 34817 ( 3.48 %) Edges 1702 out of 110193 ( 1.54 %) ex02 : i/o =25237/18422 lat = 0 nd = 33607 edge = 108491 area =33607.00 delay =308.95 lev = 13

25. Experimental Results Area-only mapping was performed using a unit-area library. Parameters of mfs3 were selected to match the runtime of amap and &nf. Each of these commands took about 3 min for all benchmarks listed.

26. Conclusion • Introduced the SAT solver as a powerful Boolean computation engine • Reviewed several SAT-based algorithms • Circuit restructuring by ISOP computation • Technology mapping based on two orthogonal approaches • Finding a better gate cover (structural mapping) • Finding a better functional expression (functional mapping) • Discussed the key difference between SAT and BDDs • And why SAT replaced BDDs in most of the application domains • Looked into some results produced by functional mapper

27. Abstract • This presentation focuses on the use of Boolean satisfiability as a computation engine in solving typical problems arising in logic synthesis and technology mapping. In particular, a new SAT-based algorithm is presented to compute canonical irredundant sums-of-products (ISOPs) similar to Minato’s well-known BDD/ZDD-based ISOP computation. In addition, two SAT-based technology mappers are discussed: a functional mapper, which exploits don't-cares of a node in the network, and a structural mapper, which searches the space of all structural covers. Both mappers take a mapped network and improve it based on a user-specified cost function. The mappers are applicable to both standard-cells and lookup tables.