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Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. Victor Khomenko , Maciej Koutny , and Alex Yakovlev University of Newcastle upon Tyne. Talk Outline. Introduction Asynchronous circuits Logic synthesis based on state graphs
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Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne
Talk Outline • Introduction • Asynchronous circuits • Logic synthesis based on state graphs • State graphs vs. net unfoldings • Logic synthesis based on net unfoldings • Experimental results • Future work
Asynchronous Circuits Asynchronous circuits – no clocks: • Low power consumption • Average-case rather than worst-case performance • Low electro-magnetic emission • Modularity – no problems with the clock skew • Hard to synthesize • The theory is not sufficiently developed • Limited tool support
Data Transceiver Device Bus d lds dsr VME Bus Controller ldtack dtack dtack- dsr+ lds+ d- lds- ldtack- ldtack+ dsr- dtack+ d+ Example: VME Bus Controller
10000 dtack- dsr+ 00100 00000 lds+ ldtack- ldtack- ldtack- dtack- dsr+ 10010 01100 01000 11000 ldtack+ lds- lds- lds- dtack- dsr+ 11010 01110 11010 M’’ M’ 01010 d+ d- dsr- dtack+ 01111 11111 11011 Example: CSC Conflict
M’’ M’ Example: Enforcing CSC dtack- dsr+ csc+ 001000 100000 000000 100001 lds+ ldtack- ldtack- ldtack- dtack- dsr+ 011000 100101 010000 110000 ldtack+ lds- lds- lds- dtack- dsr+ 110101 011100 110100 010100 d+ d- dsr- dtack+ csc- 011111 111111 110111 011110
Example: Resulting Circuit Data Transceiver Device Bus d lds dtack dsr csc ldtack
State Graphs vs. Unfoldings State Graphs: • Relatively easy theory • Many efficient algorithms • Not visual • State space explosion problem
State Graphs vs. Unfoldings Unfoldings: • Alleviate the state space explosion problem • More visual than state graphs • Proven efficient for model checking • Quite complicated theory • Not sufficiently investigated • Relatively few algorithms
DATE’02 & ACSD’03 DATE’03 ACSD’04 State Graphs vs. Unfoldings SG Unf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping Complex-gate synthesis
Synthesis using unfoldings Outline of the algorithm: for each output signal z compute (minimal) supports of z for each ‘promising’ support X compute the projection of the set of reachable encodings onto X sorting them according to the corresponding values of Nxtz apply Boolean minimization to the obtained ON- and OFF-sets choose the best implementation of z
CSCz property X • The CSC property: the next-state function of every output signal is a well-defined Boolean function of encoding of current state, i.e., all the signals can be used in its support • The CSCz property: Nxtz is a well-defined Boolean function of encoding of current state; again, all the signals can be used in its support • The CSCz property: Nxtz is a well-defined Boolean function of projection of the encoding of the current state on set of signals X; i.e., X is a support X
CSCz conflicts X • States M’ and M’’ are in CSCz conflict if • Codex(M’)=Codex(M’’) for all xX, and • Nxtz(M’) Nxtz(M’’) • Nxtz can be expressed as a Boolean function with support X iff there are no CSCz conflicts X X
M’’ X={dsr, ldtack} M’ Nxtcsc(M’)=1 Nxtcsc(M’’)=0 Example: CSCz conflict X dtack- dsr+ csc+ 001000 100000 000000 100001 lds+ ldtack- ldtack- ldtack- dtack- dsr+ 011000 100101 010000 110000 ldtack+ lds- lds- lds- dtack- dsr+ 110101 011100 110100 010100 d+ d- dsr- dtack+ csc- 011111 111111 110111 011110
dsr ldtack dtack lds d csc Code(C’) 1 1 0 1 0 1 Code(C’’) 1 1 0 0 0 0 C’ C’’ X Example: CSCz conflict in unfolding X dtack- dsr+ e14 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e12 csc+ dsr+ lds+ ldtack+ dtack+ csc+ csc- d+ dsr- d- e11 e13 lds- ldtack- Nxtcsc(C’)=1Nxtcsc(C’’)=0 Nxtcsc= dsr (ldtack csc)
Computing supports • Using unfoldings, it is possible to construct a Boolean formula CSCz(X,…)such that CSCz(X,…)[Y/X]is satisfiable iff Yis not a support • The projection of the set of satisfying assignments of CSCz(X,…)onto X is the set of all non-supports of z (it is sufficient to compute the maximal elements of this projection) • The set of supports can then be computed as { Y | YX, for all maximal non-supports X }
Outline of the algorithm for each output signal z compute (minimal) supports of z for each ‘promising’ support X compute the projection of the set of reachable encodings onto X sorting them according to the corresponding values of Nxtz apply Boolean minimization to the obtained ON- and OFF-sets choose the best implementation of z Need to know how to compute projections!
max Proj{a,b,c} a b c 0 1 1 1 0 1 min Proj{a,b,c} a b c 0 1 0 1 0 0 Example: projections a b =(a b)(a b)(c d e) a b c d e 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 Proj{a,b,c} a b c 0 1 0 0 1 1 1 0 0 1 0 1
a b (abc) (abc) (abc) (abc) 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 =(ab)(ab)(cde) 1 0 1 0 0 Computing projections Proj{a,b,c} a b c d e UNSAT • Incremental SAT
Optimizations • Triggers belong to every support – significantly improves the efficiency • Further optimizations are possible for certain net subclasses, e.g. unique-choice nets
Experimental Results • Unfoldings of STGs are almost always small in practice and thus well-suited for synthesis • Huge memory savings • Dramatic speedups • Every valid speed-independent solution can be obtained using this method, so no loss of quality • We can trade off quality for speed (e.g. consider only minimal supports): in our experiments, the solutions are the same as Petrify’s (up to Boolean minimization) • Multiple implementations produced
Future Work SG Unf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping Timing assumptions?
Thank you! Any questions?