1 / 36

Hardware Summary

Hardware Summary. Introduction. The MCS-51 is a family of microcontroller ICs developed, manufactured, and marketed by Intel. Other IC manufacturers are Siemens, Advanced Micro Devices (AMD), Fujitsu, Philips are licensed ‘second source’ suppliers of devices in the MCS-51 family.

jeffreyhudson
Download Presentation

Hardware Summary

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Hardware Summary

  2. Introduction • The MCS-51 is a family of microcontroller ICs developed, manufactured, and marketed by Intel. Other IC manufacturers are • Siemens, Advanced Micro Devices (AMD), Fujitsu, Philips are licensed ‘second source’ suppliers of devices in the MCS-51 family. • The generic MCS-51 IC is the 8051, the first device in the family offered commercially. Its features are summarized • 4KB ROM (64KB external code memory space) • 128B RAM (64KB external data memory space) • 8-bit I/O ports (4EA) • 16-bit timers (2EA) • Serial interface • Boolean processor • 210 bit-addressable locations • 4 s multiply/divide

  3. Comparison of MCS-51 ICs

  4. INT1 Note: bold-faced pin assignments for P1 and P3. INT2 Timer 1 Timer 0 Serial port T1 Timer 1 Interrupt Control Other registers 128B RAM 4KB ROM Timer 0 T0 CPU Bus Control I/O ports Serial port Oscillator P0 P1 P2 P3 TXD RXD RST ALE EA PSEN Address/data 8051 Block Diagram

  5. 30pF AD7(32) AD6(33) AD5(34) AD4(35) AD3(36) AD2(37) AD1(38) AD0(39) VCC (40) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 XTL1 (19) XTL2 (18) 30pF 8051 PSEN ALE EA RST (29) (30) (31) (9) (8) (7) (6) (5) (4) (3) (2) (1) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 RD(17) WR(16) T1(15) T0(14) INT1(13) INT0(12) TXD(11) RXD(10) P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 A15(28) A14(27) A13(26) A12(25) A11(24) A10(23) A9(22) A8(21) P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VSS(20) 8051 Pinouts Port 0 Port 1 Port 3 Port 2

  6. I/O Ports • 32 of the 8051’s 40 pins function as I/O port lines. However, 24 of these 32 lines are dual-purpose. • Dual purpose: can operate as I/O, control line, or part of address/data bus. • The 8-line in a port can be treated as a unit in interfacing to parallel devices such as printers, A/D converters, and so on. • Or, each line can operate independently in interfacing to single-bit devices such as switches, LEDs, transistors, motors, and loudspeakers.

  7. I/O Ports • Port 0 • Is a dual-purpose port on pins 32-39 of the 8051 IC. • In minimum-component designs, • It is used as a general purpose I/O port. • For larger designs with external memory, • It becomes a multiplexed address and data bus. • Port 1 • Is a dedicated I/O port on pins 1-8. • The pins are available for interfacing to external devices as required. • Port 2 • Is a dual-purpose port on pins 21-28 of the 8051 IC. • As a general purpose I/O port • Or as the high-byte of the address bus for designs with external ROM or more than 256B of RAM.

  8. I/O Ports • Port 3 • Is a dual-purpose port on pins 10-17 of the 8051 IC. • As a general purpose I/O port • These pins are multifunctional, with each having an alternate purpose related to special features of the 8051.

  9. Control Signals • PSEN (Program Store Enable) • Is an output signal on pin 29. • It is a control signal that enables external program (code) memory (ROM). • It usually connects to an EPROM’s output enable (OE) pin to permit reading of program bytes. • The PSEN signal pulses low (active stage) during the fetch stage of an instruction, which is stored in external program memory. • The binary codes of a program (opcode) are read from EPROM, travel across the data bus, and are latched into the 8051’s instruction register (IR) for decoding.

  10. Control Signals • ALE (Address Latch Enable) • Is an output signal on pin 30. • It is used for demultiplexing the address and data bus. • When port 0 is used in its alternate mode – as the data bus and low-byte of the address bus – ALE is the signal that latches the address into an external register during the first-half of a memory cycle. This done, the port 0 lines are then available for data input or output during the second-half of the memory cycle, when the data transfer takes place. • The ALE signal pulses at 1/6th the on-chip oscillator frequency and can be used as a general-purpose clock for the rest of the system.

  11. Control Signals • EA (External Access) • Is an input signal on pin 31. • Is generally tied high (5V) or low (ground). • If high • The 8051 executes programs from internal ROM when executing in the lower 4K/8K of memory. • If low • Programs execute from external memory only (and PSEN pulses low) • RST (Reset) • Is an input signal on pin 9. • When this signal is brought high for at least 2 machine cycles, the 8051 internal registers are loaded with appropriate values for an orderly system start-up. • For normal operation, RST is low.

  12. Memory Organization • Most microprocessors implement a shared memory apace for data and programs. Both the data and programs reside in the system RAM. Microcontroller, on the other hand, the control program must reside in ROM. • The internal memories consist of ROM and RAM. The RAM contains a rich arrangement of general-purpose storage, bit addressable storage, register banks, and special function registers.

  13. RAM 7F FF General-purpose RAM (80 bytes) 30 Special Function Registers (SFR) 2F Bit-addressable locations (16 bytes) 20 1F Bank registers (32 bytes) 80 00

  14. General-Purpose RAM 7F Ex: To read the contents of internal RAM address 5FH into the accumulator. Solution1:(direct address mode) MOV A, 5FH Solution2:(immediate addressing & indirect address mode) MOV R0, #5FH MOV A, @R0 General-purpose RAM (80 bytes) 30 2F 20 1F Bank registers (32 bytes) 00

  15. 210 (128+82) Bit-Addressable RAM 7F FF The idea of individually accessing bits through software is a powerful feature of most microcontroller. 30 Special Function Registers (SFR) (82 bits) 2F Bit-addressable locations (16 bytes) (128 bits) 20 1F 80 00

  16. 128 General-Purpose Bit-Addressable Locations Ex: to set bit 67H Solution: (in Microcontroller) SETB 67H Solution: (in Microprocessor) MOV A, 2CH ORL A, #10000000B MOV 2CH, A

  17. 128 General-Purpose Bit-Addressable Locations Ex: What instruction would be used to set bit 3 in byte address 25H? Solution: (in Microcontroller) SETB 2BH

  18. Register Banks Bank 3 (8 bytes) Bank 2 (8 bytes) Bank 1 (8 bytes) Bank 0 (8 bytes) Ex: Read the contents of address 05H into the accumulator. Solution: (Register address mode) MOV A, R5 (only 1-byte) Solution: (direct address mode) MOV A, 05H (2-byte instruction) Data values used frequently should use one of these registers.

  19. Register Banks Bank 3 (8 bytes) Bank 2 (8 bytes) Bank 1 (8 bytes) Bank 0 (8 bytes) Ex: What location of the following instruction writes the contents of accumulator into? SETB RS1 SETB RS0 MOV R0, A Solution: (Register address mode): 18H Select the register bank 3

  20. Register Banks Bank 3 (8 bytes) Bank 2 (8 bytes) Bank 1 (8 bytes) Bank 0 (8 bytes) Ex: What is the address of register 5 in register bank 3? Solution: (Register address mode): 1DH 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7

  21. 21 Special Function Registers (SFR)

  22. 21 Special Function Registers (SFR) Some SFRs are both bit-addressable and byte-addressable. SETB 0E0H (bit-addressable) The bits within Port 1 have addresses 90H to 97H. 10010xxxB

  23. Program Status Word (PSW) • Carry flag (CY) • Is a dual-purpose. Carry out of bit 7 during add, or borrow into bit 7 during a subtract. • EX: MOV A, #FFH ADD A, #1 • What is the state of the carry flag and the content of the accumulator after execution of the following instruction sequence? MOV R5, #55H; MOV A, #0AAH; ADD A, R5; • Solution: • A=FFH and CY=0 (No Carry) A=00H and sets the carry flag in the PSW (ie CY=1).

  24. Program Status Word (PSW) • Auxiliary Carry flag (AC) • When adding a BCD values, the AC is set if a carry was generated out of bit 3 into bit 4. • What is the state of the AC and the content of the accumulator after execution of the instruction sequence below? • MOV R5, #1; MOV A, #9; ADD A, R5; • Solution: A=10H (BCD) =1010 = 00010000B  AC=1

  25. Program Status Word (PSW) • Register bank select bit (RS1 and RS0) RS1 RS0 Register Bank # 0 0 0 0 1 1 • 0 2 1 1 3 • SETB RS1; CLR RS0;  Register Bank 2 • SETB RS1 (= SETB 0D4H) • SETB RS0 (=SETB 0D3H)

  26. Program Status Word (PSW) • Overflow Flag (OV) • When signed numbers are added or subtracted, software can examine this bit to determine if the result is in the proper range ( -128 < X < 127). • If X >=127 and X <=-128  OV=1 • MOV R7, #0FFH; MOV A, #0FH; ADD A, R7; • Solution • R7=11111111 (00000000+1=-00000001B=-1) • A=00001111 (15) • A=-1+15=14 =0EH< 127  OV=0 (No overflow)

  27. Program Status Word (PSW) • Parity bit (P) • The P is set or cleared each machine cycle to establish even parity accumulator. • MOV A, #55H • A=01010101B  numbers of 1-bit = 4  P=0

  28. B Register and Stack Pointer • B register or B accumulator • MUL AB • Results of low-byte in A and high-byte in B. • DIV AB • Integer results in A and remainder in B. • It is bit-addressable thru bit addresses F0H to F7H. • Stack Pointer (SP) • The SP is an 8-bit register at address 81H.

  29. Data Pointer (DPL, DPH) • Data pointer (DPTR) is used to access external code or data memory (16-bit register) • DPH: Data Pointer High-byte) at 83H • DPL: Data Pointer Low-byte) at 82H • EX • MOV A, #55H  A=55H • MOV DPTR, #1000H  DPTR=1000H (16-bit) • MOVX @DPTR, A  Move the content of A to the external RAM location whose address is in DPTR (1000H)

  30. Port Registers • Ports 0, 2, and 3 may not be available for I/O if external memory is used or if some of the 8051 special features are used (interrupt. Serial port etc.) • Nevertheless, P1.2 to P1.7 are always available as general purpose I/O lines. • SETB P1.7 (=SETB 97H) might turn the motor ON • CLR P1.7 (=CLR 97H) might turn the motor OFF.

  31. Timer Registers • The 8051 contains two 16-bit timer/counters for timing intervals or counting events. Timer 0 is TH0 and TL0, timer 1 is TH1 and TL1. • Timer operation is set by the timer mode register (TMOD) and timer control register (TCON). • The TCON is bit-addressable.

  32. Serial Port Registers • The 8051 contains an on-chip serial port for communicating with serial devices such as terminals or modem, or interfaces with other ICs with a serial interface (A/D converters, shift registers, nonvolatile RAM, etc.) • The SBUF (serial data buffer) at address 99H holds both the transmit data and receive data. • SCON (serial port control register) is used for various modes of operation. • SCON is a bit-addressable.

  33. Interrupt Registers • Interrupts are disabled after a system reset and then enabled by writing to the interrupt enable register (IE) at address A8H. • The priority level is set through the interrupt priority register (IP) at address B8H. • Both registers are bit-addressable.

  34. Power Control Register • SMOD: Double baud rate bit; when set, baud rate is doubled in serial port modes 1, 2, and 3. • GF1 & GF0: General-purpose flag bits 1 and 0. • PD: Power down; set to activate power down mode; only exit is reset. • The oscillator is stopped, all functions are stopped, all RAM contents are retained, port pins retain their logic levels, and ALE and PSEN are held low. VCC is 2V. • IDL: Idle mode; set to activate idle mode; only exit is an interrupt or system reset. • The internal clock signal is gated off to the CPU. The CPU status is preserved and all register contents are maintained. Port pins also retain their logic levels. ALE and PSEN are held high.

  35. Memory Cycle Address A0-A15 Non-multiplexed (24 lines) Data D0-D7 Address A8-A15 Multiplexed (16 lines) Data Address AD0-AD7 External Memory • When external memory is used, Port 0 is not available as an I/O port. It becomes a multiplexed address (A0-A7) and data (D0-D7) bus, with ALE latching the low-byte of the address at the beginning of each external memory cycle. Port 2 is usually employed for the high-byte of the address bus.

  36. 8051 EPROM D0-D7 A0-A7 A8-A15 OE Port 0 D Q EA ALE G Port 2 PSEN Accessing External Code Memory • Here’s how the multiplexed arrangement works: during the first half of each memory cycle, the low-byte of the address is provided on Port 0 and is latched using ALE. • A 74HC373 latch holds the low-byte of the address stable for the duration of the memory cycle. • During the second half of the memory cycle, Port 0 is used as the data bus, and data are read or written depending on the operation. 74HC373

More Related