Paul Scherrer Institut

1. Stefan Ritt Paul Scherrer Institut DRS Chip Developments Clermont Ferrand,

2. Agenda DRS4 chip has been developed at PSI and has been shown at this Workshop in Lyon 2008 No new chip development since 2008, but deployment of 3000 channels in the MEG experiment many chips and boards shipped worldwide Experiences in designing large systems Some new ideas about next generation DRS4 Chip Evaluation Board Clermont Ferrand,

3. DRS4 Fabricated in 0.25 mm 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins,4 ch. 2048, …, 1 ch. 8192 Differential inputs/outputs Sampling speed 500 MHz … 6 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexedor in parallel Clermont Ferrand,

4. DRS4 @ MEG LMK03000 4 x DRS4 32 channels 3000 Channels Clermont Ferrand,

5. DRS4 around the world Clermont Ferrand,

6. Worldwide Community 750 chips and 50 evaluation boards shipped worldwide Community forming sharing ideas helping each other more elaborate chip characterization helps to reduce chip prices motivate other groups to develop their own SCA Pushing the field of SCA technology forward Clermont Ferrand,

7. The problem of big systems how to synchronize? Dt=1 ps Dt=1 ps Machine RF Clermont Ferrand,

8. Jitter Measurement 1 Use LeCroy WavePro 7300A (3 GHz, 20 GSPS) with analysis statistics: Clermont Ferrand,

9. Problems Low Gain: High Gain: Not enough samplepoints in window  underestimation Scope noise (6-7 bit)leads to timing jitter  overestimation Single ended probe: 20 ps Differential probe:  2 ps Clermont Ferrand,

10. Jitter Analysis with SA carrier frequency (e.g. 20 MHz) 85 k$ Clermont Ferrand,

11. Quarz Jitter Clermont Ferrand,

12. PLL Behavior 9ps Quartz through FPGA: Improvement 9 ps  1.3 psif FPGA clockwas turned off! 23ps Quartz through DCM: Clermont Ferrand,

13. First Results Quartz FPGA DCM Clermont Ferrand,

14. Jitter with differential signals Single Ended Differential voltage noise band of signal timing jitter arising from voltage noise + - timing jitter is much smaller for faster rise-time Clermont Ferrand,

15. Differential Signals through FPGA Differential clocks won’t help! FPGA Quartz DCM VDD noise VDD/2 t t’ Clermont Ferrand,

16. DRS4 @ MEG Temperature Stabilized Master Quartz 20 MHz LVDS fan-out LVDS fan-out LVDS fan-out Is the jitter low enough or should we use a jitter cleaner? 200 low jitter LVDS lines Clermont Ferrand,

17. LMK03000 LMK03000 Clock Conditioner(National Semiconductor) Jitter: 400 fs 20 MHz 1.2 GHz 1.56 MHz 240 MHz Clermont Ferrand,

18. Measurement with test board FPGAoutput Clermont Ferrand,

19. Phase Jitter after cleaner National Semiconductor Application Note AN-1734 Clermont Ferrand,

20. Timing Big Systems II Experiment wide global clock SCAChip LMK03000 PLL Inverter Chain Channel 0 Channel 1 • Global clock locks all DRS4 PLLs to same frequency and phase • Residual PLL jitter: 25 ps • Even better timing can be obtained by direct clock sampling: 2 ps • MEG Experiment: Single LVDSclock distributed over 9 VMEcrates Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Clermont Ferrand,

21. Global Timing 1 120 120 120 EN LMK03000 DRS4 REFCLK MEG Clock 20 MHz PLL 240 MHz CH9 EN EN FPGA Clermont Ferrand,

22. Global Timing 2 120 120 120 EN LMK03000 DRS4 REFCLK MEG Clock 20 MHz PLL 240 MHz CH9 EN EN Driven by FPGA missing MEG clock FPGA Clermont Ferrand,

23. Global Timing 3 120 120 120 EN LMK03000 DRS4 REFCLK MEG Clock 20 MHz PLL 240 MHz CH9 EN EN Driven by MEG clock FPGA Clermont Ferrand,

24. Synchronization of clock chips 20 MHz 1.2 GHz 50 ns SYNC & 20 MHz 1.56 MHz Chip 1 1.56 MHz Chip 2 n * 0.83 ns • SYNC has to arrive on all board within 50 ns  trigger bus • 20 MHz MEG clock has to arrive on all boards within 0.83 ns Clermont Ferrand,

25. What we learn from LMK03000 Differential inverter chain VDD noise cancels Use only small VCO rangeLMK03000: 1185-1296 MHz Use partly internal andexternal loop filter Use separate VDD and GND for PLL use LDO on chip Consider for next generation SCA design Clermont Ferrand,

26. Away from crate-based systems G. Varner: BLAB2 readout system for f-DIRC fiber optics GBit Ethernet WaveDREAM Board (PSI) 1 k$/slot Clermont Ferrand,

27. Next Generation SCA Low parasitic input capacitance High bandwidth Large area low resistance bus, lowresistance analog switches high bandwidth Short sampling depth Deep sampling depth • Digitize long waveforms • Accommodate long trigger delay • Faster sampling speed for a given trigger latency How to combine best of both worlds? Clermont Ferrand,

28. Cascaded Switched Capacitor Arrays input shift register • 32 fast sampling cells (10 GSPS/130nm CMOS) • 100 ps sample time, 3.1 ns hold time • Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) • Shift register gets clocked by inverter chain from fast sampling stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fast sampling stage secondary sampling stage Clermont Ferrand,

29. How is timing resolution affected? voltage noise Du signal height U timing uncertainty Dt rise time tr number of samples on slope Clermont Ferrand,

30. How is timing resolution affected? today: optimized SNR: next generation: includes detector noise in the frequency region of the rise time and aperture jitter Clermont Ferrand,

31. Conclusions SCA community growing! Building big systems with O(ps) accuracy is tough but possible New generation of SCA chips on the horizon Clermont Ferrand,