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Physical Design Tools for Embedded Memories in SoC and SiP

Physical Design Tools for Embedded Memories in SoC and SiP. Yao-Wen Chang. The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei 106, Taiwan. Introduction.

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Physical Design Tools for Embedded Memories in SoC and SiP

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  1. Physical Design Tools for Embedded Memories in SoC and SiP Yao-Wen Chang The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei 106, Taiwan

  2. Introduction • With various IPs being integrated into an SoC and various dice into an SiP, the IC design and integration complexity increase drastically • Embedding a large number of memory cores in an SoC or an SiP further complicates the design complexity Memory Contents in ASIC Type SoC

  3. Challenges of Memory Design in SoC and SiP 1. Memory placement in SoC 2. Memory placement and routing of SiP Memory Bonding Wire Die (Memory) Package

  4. Memory Placement in SoC • Embedding memories into a die (Inter-die embedded memories) can get advantages compared to MCM • Increase the functionality, achieve higher performance, and optimize power • Poor floorplan and/or over-sized memory blocks typically deteriorate performance and power • Consider simultaneous memory partitioning, floorplanning, and performance/power optimization Power Memory High Low Conventional Approach Optimized Approach

  5. Problem of SoC • Problem: • Given a set of memory blocks, a set of circuit blocks, and a fixed-outline bounding core • Find a floorplan and then fit it into the package • Objectives • Optimize wirelength, power consumption, performance, and signal skew • Strip down memory blocks such that power consumption and performance are optimized Power High Low Optimized Approach

  6. Memory Placement in SiP • Can use SiP to make the integration of logic circuits and memories much more easily • May be difficult to integrate logic circuits and memories into an SoC due to different processing technologies • Memory placement (intra-die embedded memories) • Stack dice on a package • Maximize routability • Minimize total wirelength and wire crossings of fly-lines Die 1: Processor Die 2: Memory Better Order of Dice Worse Order of Dice

  7. Memory Routing in SiP (1/2) • Inter- and intra-die routing • Concentrated vertical bus • Easier for routing (shorter 2D wires), but larger capacitance • Sparse vertical bus • Lower capacitance (sparser vias), but more complicated routing Tradeoff

  8. Memory Routing in SiP (2/2) • Intra-die routing • Route bonding wires from fingers to fingers or pads • Minimize the number of wire crossings of fly-lines to increase reliability Die Bonding wire Finger Pad Package

  9. Memory Routing into SiP • Chip-package-board co-design • Give higher flexibility to design a system • Can achieve much higher performance • Assign signals and route wires from PCB to die via package (pins to fingers via pads) PCB : Fingers : Pads Die Component Pins Package

  10. SiP Research Problem 1 • Problem 1: • Given a netlist and the locations of component pins, package pads, and die fingers • Assign signals and route wires from pins to fingers via pads • Objectives • Maximize routability • Minimize total wirelength and the numbers of vias and routing layers PCB : Fingers : Pads Die Component Pins Package

  11. SiP Research Problem 2 • Problem 2: • Given a netlist, dice and fingers, and a package and pads • Place dice and route wires among dice and between dice and the package • Objectives • Maximize routability • Minimize total wirelength, wire RC delay, and the number of wire crossings of fly-lines

  12. References • [CJH+06] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high quality analytical placer considering preplaced blocks and density constraint," in Proc. ICCAD, Nov. 2006. • [CJH+06] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace2: A Hybrid Placer Using Partitioning and Analytical Techniques,” in Proc.ISPD, 2006. • [CWG+98] F. Catthoor, S. Wuytack, G.E. de Greef, F. Banica, L. Nachtergaele, and A. Vandecappelle, “Custom Memory Management Methodology,” Kluwer Academic Publishers Dordrecht, The Netherlands,1998. • [FHC+07] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer Linear Programming based Routing Algorithm for Flip-Chip Design,” in Proc. DAC, 2007. • [FLC+07] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, “A Network-Flow based RDL Routing Algorithm for Flip-Chip Design,” IEEE Tran. Computer-Aided Design, vol. 26, 2007. • [KW+01] D. Keitel-Schulz and N.Wehn. “Embedded DRAM Development: Technology, Physical Design, and Application Issues,” IEEE Design & Test of Computers, Vol.18, 2001. • [LAS+06] G. L. Loi, B. Agrawal, N. Srivastava, S.-C. Lin, T. Sherwood, and K. Banerjee, “A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy,” in Proc.DAC, 2006. • [MPK+05] E. J. Marinissen, B. Prince, D. Keitel-Schulz, and Y. Zorian, “Challenges in Embedded Memory Design and Test,” in Proc.DATE, 2005. • [NW+91] K. Nabors and J. White, “FastCap: A Multiple Accelerated 3-D Capacitance Ectraction Program,” IEEE Tran. Computer-Aided Design, Vol.10, 1991.

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